公开(公告)号：US10964363B2

公开(公告)日：2021-03-30

申请号：US16540156

申请日：2019-08-14

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Jou-Ling Chen

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.

公开(公告)号：US11373692B2

公开(公告)日：2022-06-28

申请号：US17180554

申请日：2021-02-19

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Jou-Ling Chen

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.

公开(公告)号：US10810078B2

公开(公告)日：2020-10-20

申请号：US16459621

申请日：2019-07-02

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Ching-Yeh Hsuan ,  Jou-Ling Chen

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04 ,  H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  G06F9/30

Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.

公开(公告)号：US20200012558A1

公开(公告)日：2020-01-09

申请号：US16459621

申请日：2019-07-02

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Ching-Yeh Hsuan ,  Jou-Ling Chen

IPC: G06F11/10 ,  G06F9/30

Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.