公开(公告)号：US20210295894A1

公开(公告)日：2021-09-23

申请号：US17238000

申请日：2021-04-22

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US11776613B2

公开(公告)日：2023-10-03

申请号：US17238000

申请日：2021-04-22

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US11017839B2

公开(公告)日：2021-05-25

申请号：US15862884

申请日：2018-01-05

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US10810078B2

公开(公告)日：2020-10-20

申请号：US16459621

申请日：2019-07-02

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Ching-Yeh Hsuan ,  Jou-Ling Chen

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04 ,  H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  G06F9/30

Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.

公开(公告)号：US20200012558A1

公开(公告)日：2020-01-09

申请号：US16459621

申请日：2019-07-02

Applicant: MEDIATEK INC.

Inventor： Bo-Wei Hsieh ,  Chia-Yu Chan ,  Ching-Yeh Hsuan ,  Jou-Ling Chen

IPC: G06F11/10 ,  G06F9/30

Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.