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1.发明授权公开(公告)号：US09871518B2
公开(公告)日：2018-01-16
申请号：US15247903
申请日：2016-08-25
Applicant: MEDIATEK INC.
Inventor： Shang-Pin Chen , Chia-Yu Chan , Bo-Wei Hsieh
IPC: H03K19/00 , G11C5/00 , G11C7/10 , G11C11/4074 , G06F3/06 , H03K19/0175 , H03K19/018 , H03K19/0185 , G11C5/04
CPC classification number: H03K19/0005 , G06F3/0625 , G06F3/0659 , G06F3/0683 , G11C5/04 , G11C7/1057 , G11C7/1084 , G11C11/4074 , H03K19/017545 , H03K19/01825 , H03K19/018557
Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
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公开(公告)号：US10964363B2
公开(公告)日：2021-03-30
申请号：US16540156
申请日：2019-08-14
Applicant: MEDIATEK INC.
Inventor： Bo-Wei Hsieh , Chia-Yu Chan , Jou-Ling Chen
Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
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公开(公告)号：US10141044B2
公开(公告)日：2018-11-27
申请号：US15247870
申请日：2016-08-25
Applicant: MEDIATEK INC.
Inventor： Shang-Pin Chen , Chia-Yu Chan , Bo-Wei Hsieh
IPC: G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C5/06 , G11C7/10 , G11C7/22
Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
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Patent Agency Ranking
公开(公告)号：US11373692B2
公开(公告)日：2022-06-28
申请号：US17180554
申请日：2021-02-19
Applicant: MediaTek Inc.
Inventor： Bo-Wei Hsieh , Chia-Yu Chan , Jou-Ling Chen
Abstract: A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.
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5.发明授权公开(公告)号：US10810078B2
公开(公告)日：2020-10-20
申请号：US16459621
申请日：2019-07-02
Applicant: MEDIATEK INC.
Inventor： Bo-Wei Hsieh , Chia-Yu Chan , Ching-Yeh Hsuan , Jou-Ling Chen
Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.
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6.发明申请公开(公告)号：US20200012558A1
公开(公告)日：2020-01-09
申请号：US16459621
申请日：2019-07-02
Applicant: MEDIATEK INC.
Inventor： Bo-Wei Hsieh , Chia-Yu Chan , Ching-Yeh Hsuan , Jou-Ling Chen
Abstract: A method of parity training for a dynamic random access memory, DRAM, is disclosed. The method comprises enabling a link error checking and correcting, ECC, functionality in a write operation of the DRAM, and remapping a parity function of a write parity pin to an data inversion function, a data replacing function, or a logical function, whereby data transferred to the DRAM through the write parity pin is used for indicating an inversion operation, a logical operation, or a substitution operation for data of a data pin.
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7.发明申请公开(公告)号：US20170222647A1
公开(公告)日：2017-08-03
申请号：US15247903
申请日：2016-08-25
Applicant: MEDIATEK INC.
Inventor： Shang-Pin Chen , Chia-Yu Chan , Bo-Wei Hsieh
IPC: H03K19/00 , G06F3/06 , G11C11/4074
CPC classification number: H03K19/0005 , G06F3/0625 , G06F3/0659 , G06F3/0683 , G11C5/04 , G11C7/1057 , G11C7/1084 , G11C11/4074 , H03K19/017545 , H03K19/01825 , H03K19/018557
Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.
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公开(公告)号：US20170221544A1
公开(公告)日：2017-08-03
申请号：US15247870
申请日：2016-08-25
Applicant: MEDIATEK INC.
Inventor： Shang-Pin Chen , Chia-Yu Chan , Bo-Wei Hsieh
IPC: G11C11/4076 , G11C11/4096 , G11C11/4093
CPC classification number: G11C11/4076 , G11C5/066 , G11C7/1084 , G11C7/225 , G11C11/4093 , G11C11/4096
Abstract: A memory interface circuit includes a plurality of receivers and a signal detector. The plurality of receivers are arranged for receiving at least a clock signal and a plurality of command signals from a memory controller, respectively. The signal detector is arranged for detecting whether the memory interface circuit receives the clock signal or not to generate a detection result to enable or disable the plurality of receivers.
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