公开(公告)号：US20240112963A1

公开(公告)日：2024-04-04

申请号：US18366914

申请日：2023-08-08

Applicant: MEDIATEK INC.

Inventor： Yu-Tung CHEN ,  Pei-Haw TSAO ,  Kuo-Lung FAN ,  Yuan-Fu CHUNG

IPC: H01L21/66

CPC classification number: H01L22/32

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area, a first die area and a second die area. The first die area and the second die area are separated by the scribe line area extending along a first direction. The test structure is disposed in the scribe line area. The test structure includes a test device and a first test pad. The test device has a physical characteristic similar to a semiconductor device fabricated in the first die area or the second die area. The first test pad is electrically connected to the test device. A first distance between the first test pad and the first die area gradually increases from a center region to a peripheral region of the first test pad in the first direction.

公开(公告)号：US20240178112A1

公开(公告)日：2024-05-30

申请号：US18388275

申请日：2023-11-09

Applicant: MEDIATEK INC.

Inventor： Yu-Tung CHEN ,  Kuo-Lung FAN ,  Yen-Yao CHI ,  Nai-Wei LIU ,  Pei-Haw TSAO

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor package structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor package structure also includes a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor package structure also includes a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor package structure also includes a bump structure over the RDL structure.

公开(公告)号：US20190164911A1

公开(公告)日：2019-05-30

申请号：US16157274

申请日：2018-10-11

Applicant: MEDIATEK INC.

Inventor： Chung-We PAN ,  Ching-Hung FU ,  Kuo-Lung FAN

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/765 ,  H01L29/40 ,  G01R31/28 ,  G01R27/02

Abstract: A seal ring structure is provided. The seal ring structure includes a seal ring on a semiconductor substrate. The seal ring includes a first interconnect element and a plurality of second interconnect elements. The first interconnect element is formed on a shallow trench isolation (STI) region and a first group of P-type doping regions over the semiconductor substrate. The second interconnect elements are formed below the first interconnect element and on a second group of P-type doping regions over the semiconductor substrate. The second interconnect elements are electrically separated from the first interconnect element, and the first and second groups of P-type doping regions are separated by the STI region.