公开(公告)号：US20230378971A1

公开(公告)日：2023-11-23

申请号：US18157150

申请日：2023-01-20

Applicant: MEDIATEK INC.

Inventor： Pang-Yen CHIN ,  Wei-Hsin TSENG ,  Kuan-Ta CHEN

IPC: H03M1/46

CPC classification number: H03M1/46

Abstract: A high-speed successive-approximation register analog-to-digital converter (SAR ADC) is shown. A digital-to-analog converter (DAC), a comparator, and a SAR logic circuit are configured to form a loop for successive approximation of a digital representation of an analog input. The SAR logic circuit includes a plurality of latches. Each latch uses a one-gate-delay circuit to wire the comparator to one bit-control terminal of the DAC.