公开(公告)号：US20220130814A1

公开(公告)日：2022-04-28

申请号：US17494851

申请日：2021-10-06

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Yi-Jyun Lee

IPC: H01L27/01 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

公开(公告)号：US11887976B2

公开(公告)日：2024-01-30

申请号：US17494851

申请日：2021-10-06

Applicant: MEDIATEK INC.

Inventor： Che-Hung Kuo ,  Yi-Jyun Lee

IPC: H01L23/498 ,  H01L27/01 ,  H01L25/065 ,  H01L23/58 ,  H01L49/02

CPC classification number: H01L27/01 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/585 ,  H01L28/40 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06572

Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

公开(公告)号：US12300679B2

公开(公告)日：2025-05-13

申请号：US17739295

申请日：2022-05-09

Applicant: MEDIATEK INC.

Inventor： Yi-Jyun Lee ,  Duen-Yi Ho ,  Hsing-Chih Liu ,  Che-Hung Kuo

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.