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1.发明申请METHOD FOR GENERATING A PLURALITY OF OSCILLATING SIGNALS WITH DIFFERENT PHASES AND ASSOCIATED CIRCUIT AND LOCAL OSCILLATOR 审中-公开用于产生具有不同相位和相关电路和本地振荡器的振荡信号的多项式的方法公开(公告)号：US20170012584A1
公开(公告)日：2017-01-12
申请号：US15098307
申请日：2016-04-13
Applicant: MEDIATEK INC.
Inventor： Yueh-Ting Lee , Yao-Chi Wang , Sheng-Che Tseng
CPC classification number: H03B27/00 , H03K5/14 , H03K21/02 , H03K2005/00234 , H03L7/00 , H03L7/0812
Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.
Abstract translation: 用于产生具有不同相位的多个振荡信号的电路包括分频器，第一延迟链，第二延迟链和校准电路。 分频器被布置用于对第一输入信号和第二输入信号进行分频，以产生第一分频输入信号和第二分频输入信号。 第一延迟链被布置用于延迟第一分频输入信号，并且第二延迟链被布置用于延迟第二分频输入信号。 校准电路被配置为根据第一延迟链或第二延迟链内的信号来控制第一延迟链和第二延迟链的延迟量; 其中所述第一延迟链和所述第二延迟链内的部分延迟单元的输出信号用作具有不同相位的多个振荡信号。
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公开(公告)号：US10164574B2
公开(公告)日：2018-12-25
申请号：US15098307
申请日：2016-04-13
Applicant: MEDIATEK INC.
Inventor： Yueh-Ting Lee , Yao-Chi Wang , Sheng-Che Tseng
Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.
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