公开(公告)号：US20240204897A1

公开(公告)日：2024-06-20

申请号：US18067767

申请日：2022-12-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Maciek Machnikowski ,  Wojciech Wasko ,  Bar Shapira ,  Jonathan Oliel ,  Ofir Sadeh

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.

公开(公告)号：US20240372691A1

公开(公告)日：2024-11-07

申请号：US18367383

申请日：2023-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciek Machnikowski

IPC: H04L7/00

Abstract: A system includes a device including a transmitter associated with a link coupled to the device. The device is to receive from an application layer of the device, a first bitstream for transmission. The device is to encode the first bitstream into one or more blocks and transmit the one or more data blocks via the link. The device is also to receive a second bitstream to be transmitted. The device is to encode the second bitstream into a control block and transmit the control block via the link. The control block includes a first portion of bits corresponding to a header indicating the control block includes the second bitstream and a second portion of bits including the second bitstream.

公开(公告)号：US12216489B2

公开(公告)日：2025-02-04

申请号：US18111916

申请日：2023-02-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

公开(公告)号：US20240281022A1

公开(公告)日：2024-08-22

申请号：US18111916

申请日：2023-02-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: In one embodiment, a clock synchronization system includes clock circuitry to maintain a clock running at a clock frequency, a clock controller, and a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to apply the clock update commands to the clock, store a holdover frequency command to maintain the clock during a failure of the clock update commands, apply the holdover frequency command to the clock responsively to detecting the failure.

公开(公告)号：US20240089077A1

公开(公告)日：2024-03-14

申请号：US17942899

申请日：2022-09-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciek Machnikowski

IPC: H04L7/00 ,  H04L12/18

CPC classification number: H04L7/0091 ,  H04L12/1881

Abstract: A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.