公开(公告)号：US20240231984A9

公开(公告)日：2024-07-11

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US12028155B2

公开(公告)日：2024-07-02

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US20240146431A1

公开(公告)日：2024-05-02

申请号：US17973575

申请日：2022-10-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Avi Urman ,  Natan Manevich

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.

公开(公告)号：US20240097876A1

公开(公告)日：2024-03-21

申请号：US18523991

申请日：2023-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

CPC classification number: H04L7/0091

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US20230269684A1

公开(公告)日：2023-08-24

申请号：US17675548

申请日：2022-02-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Timothy James Martin

IPC: H04W56/00

CPC classification number: H04W56/0045

Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.

公开(公告)号：US20230236624A1

公开(公告)日：2023-07-27

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04J3/0697 ,  H04J3/0682 ,  H04J3/0661 ,  H04J3/0679 ,  G06F1/12

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20230163869A1

公开(公告)日：2023-05-25

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US20220416925A1

公开(公告)日：2022-12-29

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US20220191275A1

公开(公告)日：2022-06-16

申请号：US17120313

申请日：2020-12-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avraham Ganor ,  Arnon Sattinger ,  Natan Manevich ,  Reuven Kogan ,  Artiom Tsur ,  Ariel Almog ,  Bar Shapira

IPC: H04L29/08 ,  G06F1/12 ,  G06F1/14

Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

公开(公告)号：US20250093905A1

公开(公告)日：2025-03-20

申请号：US18470452

申请日：2023-09-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Maciej Machnikowski

IPC: G06F1/12 ,  G06F13/42 ,  H04L7/033

Abstract: In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.