公开(公告)号：US09424214B2

公开(公告)日：2016-08-23

申请号：US14033470

申请日：2013-09-22

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

公开(公告)号：US20140095753A1

公开(公告)日：2014-04-03

申请号：US14033470

申请日：2013-09-22

Applicant: Mellanox Technologies Ltd.

Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口​​传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。

公开(公告)号：US09996491B2

公开(公告)日：2018-06-12

申请号：US15181436

申请日：2016-06-14

Applicant: Mellanox Technologies Ltd.

Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

IPC: G06F13/28 ,  G06F12/08 ,  G06F13/40 ,  G06F13/36 ,  G06F12/0831 ,  G06F13/42 ,  G11C7/10

CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

公开(公告)号：US20160283422A1

公开(公告)日：2016-09-29

申请号：US15181436

申请日：2016-06-14

Applicant: Mellanox Technologies Ltd.

Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

IPC: G06F13/28 ,  G06F13/42 ,  G11C7/10 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送数据分组和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口​​传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。