公开(公告)号：US20230393645A1

公开(公告)日：2023-12-07

申请号：US17893946

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ki-Jun Nam ,  Younghoon Oh

IPC: G06F1/3296 ,  G11C11/4074

CPC classification number: G06F1/3296 ,  G11C11/4074

Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.

公开(公告)号：US20210287731A1

公开(公告)日：2021-09-16

申请号：US16817095

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Younghoon Oh ,  Michael V. Ho

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  G11C7/10 ,  H03L7/081

Abstract: An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.

公开(公告)号：US11914451B2

公开(公告)日：2024-02-27

申请号：US17893946

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ki-Jun Nam ,  Younghoon Oh

IPC: G06F1/32 ,  G06F1/3296 ,  G11C11/4074

CPC classification number: G06F1/3296 ,  G11C11/4074

Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.

公开(公告)号：US11217298B2

公开(公告)日：2022-01-04

申请号：US16817095

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Younghoon Oh ,  Michael V. Ho

IPC: G11C11/4076 ,  G11C11/4096 ,  H03L7/081 ,  G11C7/10 ,  G11C11/4093

Abstract: An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.