公开(公告)号：US20180310014A1

公开(公告)日：2018-10-25

申请号：US15841624

申请日：2017-12-14

Applicant: MStar Semiconductor, Inc.

Inventor： KUAN-CHOU LEE ,  KAI-WEN CHENG ,  TAI-LAI TUNG

IPC: H04N19/44 ,  H03M13/00 ,  H04H40/90 ,  H04N5/455

CPC classification number: H04N19/44 ,  H03M7/00 ,  H03M13/6575 ,  H03M2201/4275 ,  H04H40/90 ,  H04H2201/16 ,  H04N5/455 ,  H04N21/40

Abstract: A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.

公开(公告)号：US20180159678A1

公开(公告)日：2018-06-07

申请号：US15610743

申请日：2017-06-01

Applicant: MStar Semiconductor, Inc.

Inventor： TING-NAN CHO ,  KAI-WEN CHENG ,  TAI-LAI TUNG

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L27/00 ,  H03L7/10

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

公开(公告)号：US20180123735A1

公开(公告)日：2018-05-03

申请号：US15795659

申请日：2017-10-27

Applicant: MStar Semiconductor, Inc.

Inventor： CHIA-WEI CHEN ,  KAI-WEN CHENG ,  KO-YIN LAI

IPC: H04L1/00 ,  H04B1/10 ,  G06F11/07

CPC classification number: H04L1/0061 ,  G06F11/0751 ,  H04B1/1036 ,  H04L25/03057

Abstract: An error limiting method includes: receiving a first signal and a first error signal, wherein the first error signal is associated with the first signal and a first symbol corresponding to the first signal; calculating a first magnitude value of the first signal; and decreasing an error energy of the first error signal according to the first magnitude value of the first signal to generate a second error signal, and outputting the second error signal to an error feedback circuit.