公开(公告)号：US10887221B2

公开(公告)日：2021-01-05

申请号：US16115356

申请日：2018-08-28

Applicant: MediaTek Inc.

Inventor： Chun-Yuan Chu ,  Kuo-Cheng Lu ,  Hong-Ching Chen

IPC: H04L12/721

Abstract: Examples of methods of synchronized mode of flow table and apparatus using the same are described. A method may involve receiving a first key associated with a first flow engine through a first port and a second key associated with a second flow engine through a second port. The method may also involve utilizing a match key in one or more flow entries in a flow table to obtain a first instruction for the first flow engine and a second instruction for the second flow engine.

公开(公告)号：US20150138976A1

公开(公告)日：2015-05-21

申请号：US14462575

申请日：2014-08-19

Applicant: MEDIATEK INC.

Inventor： Kuo-Cheng Lu ,  Chang-Due Young

IPC: H04L12/851 ,  H04L12/861 ,  H04L12/863

CPC classification number: H04L45/60 ,  H04L47/2441 ,  H04L47/62 ,  H04L49/1523 ,  H04L49/153 ,  H04L49/1538 ,  H04L49/1546 ,  H04L49/30 ,  H04L49/9057

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.

Abstract translation: 分组处理装置具有入口分组处理电路，出口分组处理电路和业务管理器。 入口分组处理电路处理从入口端口接收的入口分组。 出口分组处理电路处理通过出端口转发的出口分组。 流量管理器至少处理分组排队和调度。 入口分组处理电路和出口分组处理电路中的至少一个包括位于第一分组流路径的第一分组处理单元和位于第二分组流路径的第二分组处理单元。 第一分组流路径与第二分组流路径并行，第一分组处理单元的可编程性高于第二分组处理单元的可编程性。

公开(公告)号：US20160239439A1

公开(公告)日：2016-08-18

申请号：US15135479

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Kuo-Cheng Lu

IPC: G06F13/16 ,  H04L12/861 ,  H04L5/22

CPC classification number: G06F13/1647 ,  G06F13/1663 ,  H04L5/22 ,  H04L49/9036 ,  Y02D10/14

Abstract: Methods and apparatuses regarding shared buffer arbitration for packet-based switching are described. A data packet may be received by a packet buffer including a first plurality of banks of memory units and a second plurality of banks of memory units. Each memory unit may store one cell of data and accommodate one access operation in one clock cycle. In an event that the data packet includes at least two cells of data, the at least two cells of the data packet may be alternately written into at least one memory unit in the first plurality of banks of memory units and at least one memory unit in the second plurality of banks of memory units. Cells of data packets may be read from the first plurality of banks of memory units and the second plurality of banks of memory units according to a time-division multiplexing (TDM) scheme.

Abstract translation: 描述了关于基于分组交换的共享缓冲器仲裁的方法和装置。 数据分组可以由包括第一多个存储单元组和第二多个存储单元组的分组缓冲器接收。 每个存储器单元可以存储一个数据单元并且在一个时钟周期内容纳一个存取操作。 在数据分组包括至少两个数据单元的情况下，数据分组的至少两个单元可以被交替地写入到第一多个存储单元组中的至少一个存储器单元中，并且至少一个存储器单元 第二组多个存储单元。 可以根据时分复用（TDM）方案从存储器单元的第一多个存储体单元和第二多个存储器单元组读取数据分组的单元。

公开(公告)号：US20150139235A1

公开(公告)日：2015-05-21

申请号：US14469607

申请日：2014-08-27

Applicant: MEDIATEK INC.

Inventor： Kuo-Cheng Lu ,  Yi-Hung Chen ,  Chang-Due Young

IPC: H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L49/25 ,  H04L49/354

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, a traffic manager, and a processor. The ingress packet processing circuit processes an ingress packet received from an ingress port to generate at least one parameter. The egress packet processing circuit has at least one programmable look-up table, refers to the at least one parameter to determine at least one action command set, and executes the at least one action command set for generating an egress packet to be forwarded through an egress port. The traffic manager is coupled between the ingress packet processing circuit and the egress packet processing circuit. The processor programs the at least one programmable look-up table. No action command in the at least one action command set is transmitted from the ingress packet processing circuit to the egress packet processing circuit through the traffic manager.

Abstract translation: 分组处理装置具有入口分组处理电路，出口分组处理电路，业务管理器和处理器。 入口分组处理电路处理从入口端口接收的入口分组以产生至少一个参数。 出口分组处理电路具有至少一个可编程查询表，参考至少一个参数来确定至少一个动作命令集，并且执行至少一个动作命令集，用于生成要通过 出口端口 流量管理器耦合在入口分组处理电路和出口分组处理电路之间。 处理器对至少一个可编程查询表进行编程。 至少一个动作命令集中的动作命令通过流量管理器从入口分组处理电路发送到出口分组处理电路。

公开(公告)号：US09674084B2

公开(公告)日：2017-06-06

申请号：US14462575

申请日：2014-08-19

Applicant: MEDIATEK INC.

Inventor： Kuo-Cheng Lu ,  Chang-Due Young

IPC: H04L12/851 ,  H04L12/861 ,  H04L12/863 ,  H04L12/933 ,  H04L12/935 ,  H04L12/773

CPC classification number: H04L45/60 ,  H04L47/2441 ,  H04L47/62 ,  H04L49/1523 ,  H04L49/153 ,  H04L49/1538 ,  H04L49/1546 ,  H04L49/30 ,  H04L49/9057

Abstract: A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.

公开(公告)号：US20170118312A1

公开(公告)日：2017-04-27

申请号：US15402132

申请日：2017-01-09

Applicant: MediaTek Inc.

Inventor： Hong-Ching Chen ,  Kuo-Cheng Lu

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/04 ,  H04L45/74 ,  H04L67/2814 ,  H04L69/22

Abstract: Examples of packet header deflation for network virtualization are described. A method may involve receiving a data packet having a first length. The method may also involve abbreviating a header of the data packet to deflate the data packet into a deflated data packet having a second length shorter than the first length. The method may further involve forwarding the shortened data packet.

公开(公告)号：US20160314821A1

公开(公告)日：2016-10-27

申请号：US15098330

申请日：2016-04-14

Applicant: MEDIATEK INC. ,  National Chiao Tung University

Inventor： Kuo-Cheng Lu ,  Bo-Cheng Lai ,  Kun-Hua Huang ,  Jiun-Liang Lin

IPC: G11C7/10 ,  G11C11/406

CPC classification number: G11C7/1075 ,  G11C7/1006 ,  G11C16/3418

Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided, wherein the plurality of banks comprise at least a first bank, a second bank and a reference bank, and the method comprises: when first data is requested to be written into the first bank, reading reference data from the reference bank, and encoding the first data with the reference data to generate first encoded data, and writing the first encoded data into the first bank; and when second data is requested to be written into the second bank, reading the same reference data from the reference bank, and encoding the second data with the reference data to generate second encoded data, and writing the second encoded data into the second bank.

Abstract translation: 提供了一种用于访问包括多个存储体的多端口存储器模块的方法，其中所述多个存储体包括至少第一存储体，第二存储体和参考存储体，并且所述方法包括：当第一数据被请求为 写入第一组，从参考库读取参考数据，并用参考数据对第一数据进行编码，以产生第一编码数据，并将第一编码数据写入第一组; 并且当第二数据被请求写入第二组时，从参考组读取相同的参考数据，并用参考数据对第二数据进行编码，以产生第二编码数据，并将第二编码数据写入第二组。

公开(公告)号：US20160313923A1

公开(公告)日：2016-10-27

申请号：US15098336

申请日：2016-04-14

Applicant: MEDIATEK INC. ,  National Chiao Tung University

Inventor： Bo-Cheng Lai ,  Jiun-Liang Lin ,  Kuo-Cheng Lu

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0688

Abstract: A method for accessing a multi-port memory module comprising a plurality of banks is provided. In one embodiment, the method comprises: generating a plurality of parities, wherein each parity is generated according to bits of a portion of the banks; and writing the parities into the banks, respectively. In another embodiment, the method comprises: when two bits corresponding to two different addresses within a specific bank are requested to be read in response to two read commands, directly reading the bit corresponding to one of the two different address of the specific bank; and generating the bit corresponding to the other address of the specific bank by reading the bits of the other banks without the specific bank.

Abstract translation: 提供了一种用于访问包括多个存储体的多端口存储器模块的方法。 在一个实施例中，所述方法包括：产生多个奇偶校验，其中每个奇偶校验根据所述存储体的一部分的位产生; 并分别将银行写入银行。 在另一个实施例中，该方法包括：当响应于两个读命令请求读取特定组中的两个不同地址的两位时，直接读取对应于特定库的两个不同地址之一的位; 并且通过读取没有特定存储体的其他存储体的位来生成与特定存储体的另一个地址相对应的位。

公开(公告)号：US10055365B2

公开(公告)日：2018-08-21

申请号：US15135479

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Kuo-Cheng Lu

IPC: H04L12/28 ,  H04L12/56 ,  G06F13/16 ,  H04L5/22 ,  H04L12/861

CPC classification number: G06F13/1647 ,  G06F13/1663 ,  H04L5/22 ,  H04L49/9036 ,  Y02D10/14

Abstract: Methods and apparatuses regarding shared buffer arbitration for packet-based switching are described. A data packet may be received by a packet buffer including a first plurality of banks of memory units and a second plurality of banks of memory units. Each memory unit may store one cell of data and accommodate one access operation in one clock cycle. In an event that the data packet includes at least two cells of data, the at least two cells of the data packet may be alternately written into at least one memory unit in the first plurality of banks of memory units and at least one memory unit in the second plurality of banks of memory units. Cells of data packets may be read from the first plurality of banks of memory units and the second plurality of banks of memory units according to a time-division multiplexing (TDM) scheme.

公开(公告)号：US20170118140A1

公开(公告)日：2017-04-27

申请号：US15191515

申请日：2016-06-23

Applicant: MEDIATEK INC.

Inventor： Kuo-Cheng Lu

IPC: H04L12/933 ,  H04L12/741 ,  H04L12/947

CPC classification number: H04L49/15 ,  H04L45/745 ,  H04L49/25

Abstract: A network switch includes a plurality of identical dies and an interconnection network packaged in a package. The identical dies include at least a first die and a second die, each having a plurality of ingress ports used to receive ingress packets, an ingress packet processing circuit used to process the ingress packets, and a traffic manager circuit used to store packets processed by ingress packet processing circuits of the first die and the second die. The interconnection network is used to transmit an output of the ingress packet processing circuit in the first die to the traffic manager circuit of the second die, and transmit an output of the ingress packet processing circuit of the second die to the traffic manager circuit of the first die.