公开(公告)号：US10387332B1

公开(公告)日：2019-08-20

申请号：US15484283

申请日：2017-04-11

Applicant: Mellanox Technologies Ltd.

Inventor： Christopher D. Metcalf ,  Bruce Edwards ,  Anant Agarwal ,  Chyi-Chang Miao ,  Patrick Robert Griffin

IPC: G06F12/128 ,  G06F12/0862 ,  G06F12/0808 ,  G06F12/14

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

公开(公告)号：US10037299B1

公开(公告)日：2018-07-31

申请号：US15689160

申请日：2017-08-29

Applicant: Mellanox Technologies Ltd.

Inventor： Carl G. Ramey ,  Christopher D. Metcalf

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022

Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.