公开(公告)号：US11151033B1

公开(公告)日：2021-10-19

申请号：US14208405

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： David M. Wentzlaff ,  Matthew Mattina ,  Anant Agarwal

IPC: G06F12/08 ,  G06F12/0806 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/0897

Abstract: A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.

公开(公告)号：US10095543B1

公开(公告)日：2018-10-09

申请号：US14286000

申请日：2014-05-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Patrick Robert Griffin ,  Mathew Hostetter ,  Anant Agarwal ,  Chyi-Chang Miao

IPC: G06F12/08 ,  G06F9/48 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/24 ,  G06F12/14 ,  G06F12/1027

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

公开(公告)号：US10387332B1

公开(公告)日：2019-08-20

申请号：US15484283

申请日：2017-04-11

Applicant: Mellanox Technologies Ltd.

Inventor： Christopher D. Metcalf ,  Bruce Edwards ,  Anant Agarwal ,  Chyi-Chang Miao ,  Patrick Robert Griffin

IPC: G06F12/128 ,  G06F12/0862 ,  G06F12/0808 ,  G06F12/14

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

公开(公告)号：US09934010B1

公开(公告)日：2018-04-03

申请号：US14675935

申请日：2015-04-01

Applicant: Mellanox Technologies Ltd.

Inventor： Patrick Robert Griffin ,  Walter Lee ,  Anant Agarwal ,  David M. Wentzlaff

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/445 ,  G06F8/30 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/437 ,  G06F8/447 ,  G06F8/451 ,  G06F8/453 ,  G06F9/48 ,  G06F9/546 ,  G06F2209/548

Abstract: Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.