公开(公告)号：US20180349292A1

公开(公告)日：2018-12-06

申请号：US15610823

申请日：2017-06-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Gilad Tal ,  Gil Moran ,  Miriam Menes ,  Gil Kopilov ,  Shlomo Raikin

IPC: G06F12/123 ,  G06F12/0808

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.

公开(公告)号：US10789175B2

公开(公告)日：2020-09-29

申请号：US15610823

申请日：2017-06-01

Applicant: Mellanox Technologies Ltd.

Inventor： Gilad Tal ,  Gil Moran ,  Miriam Menes ,  Gil Kopilov ,  Shlomo Raikin

IPC: G06F12/123 ,  G06F12/0808

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.

公开(公告)号：US10394747B1

公开(公告)日：2019-08-27

申请号：US15609433

申请日：2017-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Carl G. Ramey ,  Gil Moran ,  Adi Menachem ,  Christopher J. Jackson ,  Ilan Pardo ,  Ariel Shahar ,  Tzuriel Katoa

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.