公开(公告)号：US20240143526A1

公开(公告)日：2024-05-02

申请号：US17976909

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

公开(公告)号：US12117948B2

公开(公告)日：2024-10-15

申请号：US17976909

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

公开(公告)号：US10394747B1

公开(公告)日：2019-08-27

申请号：US15609433

申请日：2017-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Carl G. Ramey ,  Gil Moran ,  Adi Menachem ,  Christopher J. Jackson ,  Ilan Pardo ,  Ariel Shahar ,  Tzuriel Katoa

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.