公开(公告)号：US20250054910A1

公开(公告)日：2025-02-13

申请号：US18391011

申请日：2023-12-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Huseyin Ekin Sumbul ,  Edith Dallard ,  Fan Wu ,  Huichu Liu ,  Lita Yang ,  Matheus Trevisan Moreira ,  Anuradha Krishnan ,  Gireesh Vijayakumar ,  Valerio Catalano

IPC: H01L25/065 ,  H01L25/00 ,  H10B10/00 ,  H10B80/00

Abstract: A method for three-dimensionally stacking systems on chip with face to face hybrid bonding may include providing a first die including a driver gate driving a first via ladder coupled to a first top metal layer. The method may additionally include providing a second die including a load gate coupled to a second via ladder coupled to a second top metal layer. The method may also include stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240346221A1

公开(公告)日：2024-10-17

申请号：US18436602

申请日：2024-02-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Matheus Trevisan Moreira ,  Edith Dallard ,  Huseyin Ekin Sumbul ,  Fan Wu ,  William Koven

IPC: G06F30/35 ,  G06F5/06 ,  G06F30/347

CPC classification number: G06F30/35 ,  G06F5/06 ,  G06F30/347

Abstract: A device for reducing the effects of variation in inter-die communication in 3D-stacked systems may include a die-to-die interconnect that includes a first module configured to convert data from a first synchronous domain to a dual-rail quasi-delay-insensitive format and a second module configured to convert the data from the dual-rail quasi-delay-insensitive format to a second synchronous domain. Various other devices, systems, and methods of manufacture are also disclosed.