公开(公告)号：US20250056815A1

公开(公告)日：2025-02-13

申请号：US18391007

申请日：2023-12-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Lita Yang ,  Huseyin Ekin Sumbul ,  Fan Wu ,  Edith Dallard ,  Huichu Liu ,  Daniel Henry Morris

IPC: H10B80/00 ,  G06N3/063 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method for non-uniform memory access on three-dimensionally-stacked hybrid memory may include providing a logic die including a circuit and a memory. The method may additionally include providing a plurality of memory dies including an additional memory. The method may also include stacking the logic die and the plurality of memory dies three-dimensionally using face-to-face hybrid bonds that provide non-uniform access to the additional memory by the circuit. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250054911A1

公开(公告)日：2025-02-13

申请号：US18391018

申请日：2023-12-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Huichu Liu ,  Simon James Hollis ,  Fan Wu ,  Huseyin Ekin Sumbul ,  Lita Yang ,  Edith Dallard

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

Abstract: A method for three-dimensional memory stacking may include providing a logic die including a circuit and a memory, providing a memory die including an additional memory having a same footprint as the circuit and memory in the logic die, and stacking the logic die and the memory die three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240346221A1

公开(公告)日：2024-10-17

申请号：US18436602

申请日：2024-02-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Matheus Trevisan Moreira ,  Edith Dallard ,  Huseyin Ekin Sumbul ,  Fan Wu ,  William Koven

IPC: G06F30/35 ,  G06F5/06 ,  G06F30/347

CPC classification number: G06F30/35 ,  G06F5/06 ,  G06F30/347

Abstract: A device for reducing the effects of variation in inter-die communication in 3D-stacked systems may include a die-to-die interconnect that includes a first module configured to convert data from a first synchronous domain to a dual-rail quasi-delay-insensitive format and a second module configured to convert the data from the dual-rail quasi-delay-insensitive format to a second synchronous domain. Various other devices, systems, and methods of manufacture are also disclosed.

公开(公告)号：US20250054910A1

公开(公告)日：2025-02-13

申请号：US18391011

申请日：2023-12-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Huseyin Ekin Sumbul ,  Edith Dallard ,  Fan Wu ,  Huichu Liu ,  Lita Yang ,  Matheus Trevisan Moreira ,  Anuradha Krishnan ,  Gireesh Vijayakumar ,  Valerio Catalano

IPC: H01L25/065 ,  H01L25/00 ,  H10B10/00 ,  H10B80/00

Abstract: A method for three-dimensionally stacking systems on chip with face to face hybrid bonding may include providing a first die including a driver gate driving a first via ladder coupled to a first top metal layer. The method may additionally include providing a second die including a load gate coupled to a second via ladder coupled to a second top metal layer. The method may also include stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11953966B1

公开(公告)日：2024-04-09

申请号：US17721252

申请日：2022-04-14

Applicant: Meta Platforms Technologies, LLC

Inventor： Fan Wu ,  Edith Dallard

IPC: G06F1/00 ,  G06F1/3237 ,  G06F15/80 ,  G06F1/3203

CPC classification number: G06F1/3237 ,  G06F15/8046 ,  G06F1/3203

Abstract: Methods and corresponding systems and apparatuses for saving power through selectively disabling clock signals in a systolic array are described. In some embodiments, a clock gate controller is operable to output a gated clock signal from which local clock signals of processing elements in the systolic array are derived. The gated clock signal corresponds to a root clock signal that is distributed through a clock distribution network or clock tree. The clock gate controller is located along one branch of the clock distribution network. The branch can be associated with processing elements that form a column within the systolic array. Disabling the gated clock signal disables the local clock signals along the entire branch, preventing any components that are clocked by those local clock signals from consuming power. Additional clock gate controllers can similarly be provided for other branches, including a branch associated with another column.