公开(公告)号：US20250054910A1

公开(公告)日：2025-02-13

申请号：US18391011

申请日：2023-12-20

Applicant: Meta Platforms Technologies, LLC

Inventor： Huseyin Ekin Sumbul ,  Edith Dallard ,  Fan Wu ,  Huichu Liu ,  Lita Yang ,  Matheus Trevisan Moreira ,  Anuradha Krishnan ,  Gireesh Vijayakumar ,  Valerio Catalano

IPC: H01L25/065 ,  H01L25/00 ,  H10B10/00 ,  H10B80/00

Abstract: A method for three-dimensionally stacking systems on chip with face to face hybrid bonding may include providing a first die including a driver gate driving a first via ladder coupled to a first top metal layer. The method may additionally include providing a second die including a load gate coupled to a second via ladder coupled to a second top metal layer. The method may also include stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11868281B2

公开(公告)日：2024-01-09

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

CPC classification number: G06F13/1626 ,  G02B27/0172 ,  G06F3/011 ,  G06F13/161 ,  G06F13/1642 ,  G06T19/006 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

公开(公告)号：US11797451B1

公开(公告)日：2023-10-24

申请号：US17502967

申请日：2021-10-15

Applicant: Meta Platforms Technologies, LLC

Inventor： Sridhar Gurumurthy Isukapalli Sharma ,  Valerio Catalano

IPC: G06F12/084 ,  G06F12/02 ,  G06F15/78 ,  G06F12/1045

CPC classification number: G06F12/084 ,  G06F12/0238 ,  G06F12/1054 ,  G06F12/1063 ,  G06F15/7807

Abstract: The disclosure is directed to techniques for dynamically managing memory in mixed mode cache and shared memory systems. For example, a system on a chip (SoC) comprises: a plurality of memories, including a first memory and a second memory, where each of the memories includes one or more cache lines; a first subsystem comprising a first compute element and the first memory; a second subsystem comprising a second compute element and the second memory; and a memory control unit of the SoC comprising processing circuitry and configured to: configure a shared memory with one or more cache lines of at least one of the plurality of memories; and flush, based on one or more tag control bits for the one or more cache lines of the shared memory, data from the shared memory to a backend storage separate from the SoC.

公开(公告)号：US20220391331A1

公开(公告)日：2022-12-08

申请号：US17818196

申请日：2022-08-08

Applicant: Meta Platforms Technologies, LLC

Inventor： Alok Kumar Mathur ,  Ennio Salemi ,  Drew Eric Wingard ,  Valerio Catalano

IPC: G06F13/16 ,  G06T19/00 ,  G02B27/01 ,  G06F3/01 ,  G06V20/20

Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.