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    Data-driven column-wise clock gating of systolic arrays
    2.
    发明授权
    Data-driven column-wise clock gating of systolic arrays 有权

    公开(公告)号：US11953966B1

    公开(公告)日：2024-04-09

    申请号：US17721252

    申请日：2022-04-14

    Applicant: Meta Platforms Technologies, LLC

    Inventor： Fan Wu ,  Edith Dallard

    IPC: G06F1/00 ,  G06F1/3237 ,  G06F15/80 ,  G06F1/3203

    CPC classification number: G06F1/3237 ,  G06F15/8046 ,  G06F1/3203

    Abstract: Methods and corresponding systems and apparatuses for saving power through selectively disabling clock signals in a systolic array are described. In some embodiments, a clock gate controller is operable to output a gated clock signal from which local clock signals of processing elements in the systolic array are derived. The gated clock signal corresponds to a root clock signal that is distributed through a clock distribution network or clock tree. The clock gate controller is located along one branch of the clock distribution network. The branch can be associated with processing elements that form a column within the systolic array. Disabling the gated clock signal disables the local clock signals along the entire branch, preventing any components that are clocked by those local clock signals from consuming power. Additional clock gate controllers can similarly be provided for other branches, including a branch associated with another column.

    SRAM design for energy efficient sequential access
    7.
    发明授权
    SRAM design for energy efficient sequential access 有权

    公开(公告)号：US12068054B2

    公开(公告)日：2024-08-20

    申请号：US17737820

    申请日：2022-05-05

    Applicant: Meta Platforms Technologies, LLC

    Inventor： Huichu Liu ,  Daniel Henry Morris ,  Edith Dallard

    IPC: G11C8/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/18

    CPC classification number: G11C7/1093 ,  G11C7/1048 ,  G11C7/1066 ,  G11C7/12 ,  G11C8/08 ,  G11C8/18

    Abstract: An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.

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