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    Compiled self-resetting CMOS logic array macros
    2.
    发明授权
    Compiled self-resetting CMOS logic array macros 失效
    编译自复位CMOS逻辑阵列宏

    公开(公告)号：US6005416A

    公开(公告)日：1999-12-21

    申请号：US850190

    申请日：1997-05-02

    申请人： Michael Patrick Beakes ,  Barbara Alana Chappell ,  Terry Ivan Chappell ,  Gary S. Ditlow ,  Barry Lee Dorfman ,  Bruce Martin Fleischer ,  Vinod Narayanan ,  David James Widiger

    发明人： Michael Patrick Beakes ,  Barbara Alana Chappell ,  Terry Ivan Chappell ,  Gary S. Ditlow ,  Barry Lee Dorfman ,  Bruce Martin Fleischer ,  Vinod Narayanan ,  David James Widiger

    IPC分类号： H03K19/173 ,  H03K19/096

    CPC分类号： H03K19/1736

    摘要： A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

    摘要翻译： 逻辑电路系列实现了自复位CMOS逻辑阵列宏（SLAM），其包括可以应用多个数据输入信号的多个输入; 耦合以从输入接收输入信号的多个输入缓冲器; NOR电路，其耦合以接收输入缓冲器的输出;以及脉冲逻辑定时信号，在数据输入信号的到达之前在预定窗口内同步; 耦合以接收所述NOR电路的输出的输出缓冲器; 以及产生数据输出信号的输出，其中输出信号是数据输入信号的逻辑NOR; 并且与NOR电路，多个输入缓冲器和输出缓冲器中的每一个可选地具有单独的复位输入以将其复位到待机状态。 SLAM解决了控制逻辑和控制逻辑设计系统性能的巨大压力。 SLAM的独特特征被独特地组合在一起，允许从逻辑描述和接口规范自动设计满足预定设计指南的完整宏。

    Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
    3.
    发明授权
    Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects 失效
    对逻辑电路块进行建模的方法和系统，包括晶体管栅极电容负载效应

    公开(公告)号：US07552040B2

    公开(公告)日：2009-06-23

    申请号：US10366439

    申请日：2003-02-13

    申请人： Barry Lee Dorfman ,  Thomas Edward Rosser ,  Jeffrey Paul Soreff

    发明人： Barry Lee Dorfman ,  Thomas Edward Rosser ,  Jeffrey Paul Soreff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

    摘要翻译： 用于对包括晶体管栅极电容负载效应的逻辑电路块进行建模的方法和系统提供了对逻辑电路块转换时间和延迟时间的改进的仿真。 通过转换时间函数和延迟时间函数考虑连接到逻辑电路块输出的其他逻辑电路块输入的晶体管栅极的非线性行为，其分别取决于静态电容和晶体管栅极电容， 可用于确定逻辑电路块的时序和输出性能。 单独的N沟道和P沟道栅极电容也可以用作转换时间和延迟时间函数的输入以提供进一步的改进，或者N沟道与P沟道电容的比率可以替代地用作 转换时间和延迟时间功能。

    Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements
    4.
    发明申请
    Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements 有权
    在互连电气元件存在下的静态时序分析的时序点选择

    公开(公告)号：US20110167395A1

    公开(公告)日：2011-07-07

    申请号：US12652338

    申请日：2010-01-05

    申请人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

    发明人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

    摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。

    TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS
    5.
    发明申请
    TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS 审中-公开
    计算电路块延迟和过渡时间的技术，包括晶闸管电容负载效应

    公开(公告)号：US20080177517A1

    公开(公告)日：2008-07-24

    申请号：US12055852

    申请日：2008-03-26

    申请人： Barry Lee Dorfman ,  Thomas Edward Rosser ,  Jeffrey Paul Soreff

    发明人： Barry Lee Dorfman ,  Thomas Edward Rosser ,  Jeffrey Paul Soreff

    IPC分类号： G06F17/11

    CPC分类号： G06F17/5036

    摘要： Techniques for modeling delay and transition times of logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

    摘要翻译： 用于建模包括晶体管栅极电容负载效应的逻辑电路块的延迟和转换时间的技术提供了逻辑电路块转换时间和延迟时间的改进的仿真。 通过转换时间函数和延迟时间函数考虑连接到逻辑电路块输出的其他逻辑电路块输入的晶体管栅极的非线性行为，其分别取决于静态电容和晶体管栅极电容， 可用于确定逻辑电路块的时序和输出性能。 单独的N沟道和P沟道栅极电容也可以用作转换时间和延迟时间函数的输入以提供进一步的改进，或者N沟道与P沟道电容的比率可以替代地用作 转换时间和延迟时间功能。

    Timing point selection for a static timing analysis in the presence of interconnect electrical elements
    6.
    发明授权
    Timing point selection for a static timing analysis in the presence of interconnect electrical elements 有权
    在存在互连电气元件的情况下进行静态时序分析的时序点选择

    公开(公告)号：US08201120B2

    公开(公告)日：2012-06-12

    申请号：US12652338

    申请日：2010-01-05

    申请人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

    发明人： Jeffrey P. Soreff ,  Barry Lee Dorfman ,  Jeffrey G. Hemmett ,  Ravichander Ledalla ,  Vasant Rao ,  Fred Lei Yang

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5031

    摘要： A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

    摘要翻译： 一种用于选择电气互连网络中用于静态时序分析的电气仿真中的定时点的方法和系统，以提高精度。 本发明的方法包括发现在互连的电气模型中的阻塞点，所述互连的所有路径对于所述路由器必须在某些类型的网络上通过。 然后，该方法使用其存在的阻塞点电子节点作为驱动网络的逻辑门的输出定时点。 该方法解决了由于同一互连网上的不同驱动器引脚之间的电阻引起的不准确性的问题，尽管它也可以应用于解决由于与相同接收器定时点相关联的不同接收器引脚之间的电阻引起的类似不准确性。 它还适用于与其他双端口寄生元件的互连，仅在网络上的接收器引脚的子集需要精确的定时的情况下，以及一组电气节点而不是单个节点将所有路径从 驱动程序到网络上的接收器。

    Method and apparatus for detecting and correcting inaccuracies in curve-fitted models
    7.
    发明授权
    Method and apparatus for detecting and correcting inaccuracies in curve-fitted models 失效
    用于检测和纠正曲线拟合模型中的不准确度的方法和装置

    公开(公告)号：US07194394B2

    公开(公告)日：2007-03-20

    申请号：US09999141

    申请日：2001-11-15

    申请人： Barry Lee Dorfman ,  Thomas Edward Rosser

    发明人： Barry Lee Dorfman ,  Thomas Edward Rosser

    IPC分类号： G06G7/48

    CPC分类号： G06F17/17

    摘要： A technique for detecting and correcting inaccuracies in curve-fitted models. Humps and dips in a curve-fitted model are identified. An analysis is performed on the humps and dips to determine if they are large enough to warrant correction. If so, then the source of the simulation and/or empirical data is modified to taking corrective action to improve the curve fit between the edge point and the next actual simulation and/or empirical data point.

    摘要翻译： 一种用于检测和校正曲线拟合模型中的不准确度的技术。 识别曲线拟合模型中的臀部和臀部。 对隆起和下降进行分析，以确定它们是否足够大以保证校正。 如果是这样，那么模拟和/或经验数据的来源被修改以采取纠正措施来改善边缘点和下一个实际模拟和/或经验数据点之间的曲线拟合。