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    System and method for high frequency stall design
    3.
    发明授权
    System and method for high frequency stall design 失效
    高频失速设计系统及方法

    公开(公告)号：US07370176B2

    公开(公告)日：2008-05-06

    申请号：US11204414

    申请日：2005-08-16

    申请人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

    发明人： Jonathan James DeMent ,  Kurt Alan Feiste ,  Robert Alan Philhower ,  David Shippy

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3875

    摘要： A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructions located in the first instruction stage are moved to a second instruction stage, and 2) the issue control logic determines whether to issue or stall the instructions that are moved to the second instruction stage based upon their particular instruction attributes and the issue control unit's previous state. During a second instruction cycle that immediately follows the first instruction cycle, the second instruction stage's instructions are either issued or stalled based upon the issue control logic's decision from the first instruction cycle.

    摘要翻译： 提出了一种用于高频失速设计的系统和方法。 发行单元包括第一指令阶段，第二指令阶段和发布控制逻辑。 在第一指令周期期间，发行单元执行两个任务，即1）位于第一指令阶段的指令移动到第二指令阶段，2）发行控制逻辑确定是否发出或停止指令 基于其特定的指令属性和发布控制单元的先前状态，移动到第二指令阶段。 在紧随第一指令周期的第二指令周期中，基于从第一指令周期的发布控制逻辑的判定，发出或停止第二指令级的指令。

    4:2 compressor circuit for use in an arithmetic unit
    4.
    发明授权
    4:2 compressor circuit for use in an arithmetic unit 失效
    4：2用于运算单元的压缩机电路

    公开(公告)号：US06711633B2

    公开(公告)日：2004-03-23

    申请号：US10059607

    申请日：2002-01-30

    申请人： Douglas Hooker Bradley ,  Tai Anh Cao ,  Robert Alan Philhower ,  Wai Yin Wong

    发明人： Douglas Hooker Bradley ,  Tai Anh Cao ,  Robert Alan Philhower ,  Wai Yin Wong

    IPC分类号： G06F300

    CPC分类号： G06F7/607 ,  G06F7/5318

    摘要： A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate. In one embodiment, the first stage, second stage, carry circuit, and sum circuit are comprised primarily of such transmission gates to the exclusion of conventional CMOS complementary passgate logic.

    摘要翻译： 适用于微处理器运算单元的压缩机电路包括第一级，第二级，进位电路和和电路。 第一级被配置为接收一组四个输入信号。 第一级产生指示第一对输入信号的XNOR的第一中间信号和指示第二对输入信号的XNOR的第二中间信号。 第二级被配置为接收由第一级产生的信号的至少一部分。 第二级产生第一和第二控制信号，其中第一控制信号指示四个输入信号的XNOR，第二控制信号是第一信号的逻辑补码。 进位电路被配置为接收至少一个控制信号，并且还被配置为至少部分地基于所接收的控制信号的状态来产生进位位。 总和电路被配置为接收至少一个控制信号，并且还被配置为至少部分地基于所接收的控制信号的状态来产生和位。 第一级，第二级，和电路和进位电路中的至少一个包括由n沟道晶体管和p沟道晶体管组成的至少一个CMOS传输门，其源极/漏极端子并联连接，其中p 通道晶体管栅极由n沟道晶体管栅极的逻辑补码驱动。 在一个实施例中，第一级，第二级，进位电路和和电路主要由这样的传输门组成，以排除常规CMOS互补门极逻辑。

    Time-of-life counter for handling instruction flushes from a queue
    5.
    发明授权
    Time-of-life counter for handling instruction flushes from a queue 有权
    处理指令的生命周期计数器从队列中刷新

    公开(公告)号：US07913070B2

    公开(公告)日：2011-03-22

    申请号：US12250285

    申请日：2008-10-13

    申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    IPC分类号： G06F7/38

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

    摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

    摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

    Alignment of Cache Fetch Return Data Relative to a Thread
    6.
    发明申请
    Alignment of Cache Fetch Return Data Relative to a Thread 有权
    缓存提取的对齐返回相对于线程的数据

    公开(公告)号：US20090063818A1

    公开(公告)日：2009-03-05

    申请号：US11850410

    申请日：2007-09-05

    申请人： Michael Karl Gschwind ,  Hans Mikael Jacobson ,  Robert Alan Philhower

    发明人： Michael Karl Gschwind ,  Hans Mikael Jacobson ,  Robert Alan Philhower

    IPC分类号： G06F9/40

    CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3814 ,  G06F12/0859

    摘要： A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed.

    摘要翻译： 一种获得数据的方法，包括至少一个扇区，供至少第一线程使用，其中每个处理器周期被分配给至少一个线程，包括以下步骤：请求至少第一线程的数据; 在接收到所述数据的至少第一扇区时，确定所述至少第一扇区是否与所述至少第一线程对准，其中当给定扇区将被写入的处理器周期时，给定扇区与给定线程对准 被分配给给定的线程; 响应于确定所述至少第一扇区与所述至少第一线程对准，绕过所述至少第一扇区，其中旁路扇区包括在被写入时读取扇区; 并且响应于确定所述至少第一扇区不与所述至少第一线程对准，延迟所述至少第一扇区的写入，直到通过保留所述至少第一线程来分配给所述至少第一线程的处理器周期的发生 在至少一个对准寄存器中的扇区，从而允许所述至少第一扇区被旁路。

    Time-of-life counter design for handling instruction flushes from a queue
    7.
    发明授权
    Time-of-life counter design for handling instruction flushes from a queue 失效
    处理指令从队列刷新的生命周期计数器设计

    公开(公告)号：US07490224B2

    公开(公告)日：2009-02-10

    申请号：US11246587

    申请日：2005-10-07

    申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

    摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

    摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。

    Dynamic power management in a processor design
    9.
    发明授权
    Dynamic power management in a processor design 有权
    处理器设计中的动态电源管理

    公开(公告)号：US07681056B2

    公开(公告)日：2010-03-16

    申请号：US12130736

    申请日：2008-05-30

    申请人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    发明人： Christopher Michael Abernathy ,  Jonathan James DeMent ,  Ronald Hall ,  Robert Alan Philhower ,  David Shippy

    IPC分类号： G06F1/32 ,  G06F1/00 ,  G06F1/26 ,  G06F9/00

    CPC分类号： G06F1/3237 ,  G06F1/3228 ,  G06F1/3243 ,  G06F9/3867 ,  Y02D10/128 ,  Y02D10/152

    摘要： Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.

    摘要翻译： 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。

    METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM
    10.
    发明申请
    METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM 审中-公开
    方法和装置在信息处理系统的多线程处理器中增加对冲洗信息的响应优先级

    公开(公告)号：US20090193240A1

    公开(公告)日：2009-07-30

    申请号：US12023028

    申请日：2008-01-30

    申请人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

    发明人： Michael Karl Gschwind ,  Robert Alan Philhower ,  Raymond Cheung Yeung

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3842

    摘要： An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array.

    摘要翻译： 信息处理系统采用包括线程优先级控制器的处理器。 处理器包括存储包括分支指令的指令线程的存储器阵列。 当特定指令线程中的特定分支指令需要刷新操作时，处理器中的分支单元向线程优先级控制器发送刷新信息。 刷新信息可以指示特定分支指令的分支预测的不正确性的正确性，并且因此表明刷新操作的必要性。 刷新信息还可以包括特定线程的线程ID。 如果特定线程的特定分支指令的刷新信息指示需要刷新操作，则线程优先级控制器响应地推测地增加或提高包括特定分支指令的特定指令线程的优先级。 以这种方式，处理器中的提取器获得对存储器阵列中的特定线程的即时访问。