公开(公告)号：US09842071B2

公开(公告)日：2017-12-12

申请号：US14538133

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： James Casady ,  Rodney Pesavento ,  Sergey Pavlov

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/1673 ,  G06F13/385 ,  G06F13/4282 ,  G06F13/4291

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

公开(公告)号：US20160132440A1

公开(公告)日：2016-05-12

申请号：US14538133

申请日：2014-11-11

Applicant: Microchip Technology Incorporated

Inventor： James Casady ,  Rodney Pesavento ,  Sergey Pavlov

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/385 ,  G06F13/4282 ,  G06F13/4291

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Abstract translation: 串行外设接口可配置为在I2S传输模式下工作。 接口具有与外部引脚连接的传输单元，用于数据，位时钟和左/右时钟信号，具有多条存储器线的先进先出（FIFO）缓冲器，以及可操作以读取数据的控制单元 来自两个存储器线的部分，以将它们组装成传输字，并将组装的传输字转发到传输单元，其中传输单元被配置为通过外部数据引脚串行传输组装的传输字。