公开(公告)号：US12189949B2

公开(公告)日：2025-01-07

申请号：US18049121

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Tommaso Vali ,  Walter Di Francesco ,  Luigi Pilolli ,  Angelo Covello ,  Andrea D'Alessandro ,  Agostino Macerola ,  Cristina Lattaro ,  Claudia Ciaschi

IPC: G06F3/06

Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

公开(公告)号：US20240231670A1

公开(公告)日：2024-07-11

申请号：US18509587

申请日：2023-11-15

Applicant: Micron Technology, Inc.

Inventor： Angelo Covello ,  Claudia Ciaschi ,  Michele Incarnati ,  Tommaso Vali

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory device includes a local memory to store operational data and comparison logic operatively coupled with the local memory. The comparison logic, upon initialization of the memory device, compares, to detect any errors in the operational data, one copy of a first copy pair with one copy of a second copy pair of the operational data, the first copy pair including a first copy and an inverted first copy and the second copy pair including a second copy and an inverted second copy of the operational data. The comparison logic further reports an error in response to detecting the first copy pair does not match the second copy pair.