公开(公告)号：US09147729B2

公开(公告)日：2015-09-29

申请号：US14189296

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

Abstract translation: 一些实施例包括形成晶体管的方法。 凹部形成为延伸到半导体材料中。 这些凹槽具有内衬有衬垫材料的上部区域，并且具有沿下部区域暴露的半导体材料段。 半导体材料通过暴露的部分进行各向同性蚀刻，该部分将凹陷转变成在较窄上部区域下方具有较宽的较低区域的开口。 栅介电材料沿着开口的侧壁形成。 栅极材料形成在开口之间的开口和半导体材料的开口之间的区域上。 绝缘材料沿着每个开口的中心形成并完全通过栅极材料形成。 栅极材料的一段从一个开口延伸到另一个，并且在开口之间缠绕半导体材料的柱。 该段是晶体管的栅极。 源极/漏极区域形成在栅极的相对侧上。

公开(公告)号：US20150243734A1

公开(公告)日：2015-08-27

申请号：US14189296

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

Abstract translation: 一些实施例包括形成晶体管的方法。 凹部形成为延伸到半导体材料中。 这些凹槽具有内衬有衬垫材料的上部区域，并且具有沿下部区域暴露的半导体材料段。 半导体材料通过暴露的部分进行各向同性蚀刻，该部分将凹陷转变成在较窄上部区域下方具有较宽的较低区域的开口。 栅介电材料沿着开口的侧壁形成。 栅极材料形成在开口之间的开口和半导体材料的开口之间的区域上。 绝缘材料沿着每个开口的中心形成并完全通过栅极材料形成。 栅极材料的一段从一个开口延伸到另一个，并且在开口之间缠绕半导体材料的柱。 该段是晶体管的栅极。 源极/漏极区域形成在栅极的相对侧上。

公开(公告)号：US20160093709A1

公开(公告)日：2016-03-31

申请号：US14964923

申请日：2015-12-10

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L27/10805 ,  H01L27/10823 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.

公开(公告)号：US09240477B2

公开(公告)日：2016-01-19

申请号：US14189808

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L27/10805 ,  H01L27/10823 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.

Abstract translation: 一些实施例包括在半导体材料的开口内具有栅极材料并且通过栅极电介质材料与半导体材料隔开的含晶体管的构造。 开口在狭窄的上部区域下方具有较宽的较低区域。 栅介电材料的鞍形区域从开口的底部向外延伸并且沿开口下方的半导体材料延伸。 栅极材料的鞍形区域从开口的底部向外延伸并且沿开口下方的栅极电介质材料延伸。 源极/漏极区域沿着栅极材料侧面的半导体材料内。 一些实施例包括存储器阵列。

公开(公告)号：US20150243782A1

公开(公告)日：2015-08-27

申请号：US14189808

申请日：2014-02-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L27/10805 ,  H01L27/10823 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.

Abstract translation: 一些实施例包括在半导体材料的开口内具有栅极材料并且通过栅极电介质材料与半导体材料隔开的含晶体管的构造。 开口在狭窄的上部区域下方具有较宽的较低区域。 栅介电材料的鞍形区域从开口的底部向外延伸并且沿开口下方的半导体材料延伸。 栅极材料的鞍形区域从开口的底部向外延伸并且沿开口下方的栅极电介质材料延伸。 源极/漏极区域沿着栅极材料侧面的半导体材料内。 一些实施例包括存储器阵列。