公开(公告)号：US10937517B1

公开(公告)日：2021-03-02

申请号：US16685186

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Eric J. Rich-Plotkin ,  Christopher G. Wieduwilt ,  Boon Hor Lam ,  Greg S. Hendrix ,  Shawn M. Hilde ,  Jiyun Li ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C29/30 ,  G11C29/12 ,  G11C29/02 ,  H03M13/29 ,  G11C11/56 ,  G11C29/44

Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.