公开(公告)号：US12170107B2

公开(公告)日：2024-12-17

申请号：US17808818

申请日：2022-06-24

Applicant: Micron Technology, Inc.

Inventor： Shawn M. Hilde ,  Dennis G. Montierth ,  Garth N. Grubb

IPC: G11C11/406

Abstract: Methods, systems, and devices for a self-refresh state with decreased power consumption are described. A memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. Based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. Additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. In cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.

公开(公告)号：US10998022B2

公开(公告)日：2021-05-04

申请号：US16543240

申请日：2019-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Travis Marley

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/406 ,  G11C11/408

Abstract: In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to the subword driver and configured to provide the default VNWL or the reduced voltage VNWL to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.

公开(公告)号：US10937517B1

公开(公告)日：2021-03-02

申请号：US16685186

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Eric J. Rich-Plotkin ,  Christopher G. Wieduwilt ,  Boon Hor Lam ,  Greg S. Hendrix ,  Shawn M. Hilde ,  Jiyun Li ,  Dennis G. Montierth

IPC: G11C7/00 ,  G11C29/30 ,  G11C29/12 ,  G11C29/02 ,  H03M13/29 ,  G11C11/56 ,  G11C29/44

Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.

公开(公告)号：US11468960B2

公开(公告)日：2022-10-11

申请号：US16839371

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10 ,  G11C29/14

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

公开(公告)号：US20210202023A1

公开(公告)日：2021-07-01

申请号：US16839371

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10 ,  G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

公开(公告)号：US20210050042A1

公开(公告)日：2021-02-18

申请号：US16543240

申请日：2019-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Travis Marley

IPC: G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/406

Abstract: In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to die subword driver and configured to provide the default VNWL or the reduced voltage VNWL. to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.

公开(公告)号：US20250078898A1

公开(公告)日：2025-03-06

申请号：US18952772

申请日：2024-11-19

Applicant: Micron Technology, Inc.

Inventor： Shawn M. Hilde ,  Dennis G. Montierth ,  Garth N. Grubb

IPC: G11C11/406

Abstract: Methods, systems, and devices for a self-refresh state with decreased power consumption are described. A memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. Based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. Additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. In cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.

公开(公告)号：US20230420023A1

公开(公告)日：2023-12-28

申请号：US17808818

申请日：2022-06-24

Applicant: Micron Technology, Inc.

Inventor： Shawn M. Hilde ,  Dennis G. Montierth ,  Garth N. Grubb

IPC: G11C11/406

CPC classification number: G11C11/40615

Abstract: Methods, systems, and devices for a self-refresh state with decreased power consumption are described. A memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. Based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. Additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. In cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.

公开(公告)号：US20230014661A1

公开(公告)日：2023-01-19

申请号：US17935057

申请日：2022-09-23

Applicant: Micron Technology, Inc.

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10 ,  G11C29/14

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.