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公开(公告)号：US11978521B2
公开(公告)日：2024-05-07
申请号：US17937532
申请日：2022-10-03
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a fuse, a first driver circuit, and a second driver circuit. The fuse is configured to store a bit of information. The first driver circuit includes a first input terminal electrically connected to the fuse and a first output terminal electrically connected to a first latch input terminal. The second driver circuit includes a second input terminal electrically connected to the fuse and a second output terminal electrically connected to a second latch input terminal. The second latch input terminal is electrically isolated from the first latch input terminal by the first driver circuit and the second driver circuit.
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公开(公告)号：US20220068415A1
公开(公告)日：2022-03-03
申请号：US17003363
申请日：2020-08-26
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a dual interlock storage cell (DICE) latch circuit including a first input node corresponding to a first path and a second input node corresponding to a second path. The first input node is electrically isolated from the second input node.
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公开(公告)号：US12211545B2
公开(公告)日：2025-01-28
申请号：US17845640
申请日：2022-06-21
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
IPC: G11C11/4093
Abstract: Devices and methods include generating biases for input buffers of a semiconductor device. In some embodiments, the semiconductor device includes an input buffer that buffer datas and biasing generation and distribution circuitry that generates and distributes a bias current to the input buffer based at least in part on a reference voltage. The biasing generation and distribution circuitry includes dynamic voltage bias circuitry that adjusts the bias current and reference voltage tracking circuitry that controls operation of the dynamic voltage bias circuitry based on the reference voltage.
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公开(公告)号：US20230410888A1
公开(公告)日：2023-12-21
申请号：US17845640
申请日：2022-06-21
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
IPC: G11C11/4093
CPC classification number: G11C11/4093
Abstract: Devices and methods include generating biases for input buffers of a semiconductor device. In some embodiments, the semiconductor device includes an input buffer that buffer datas and biasing generation and distribution circuitry that generates and distributes a bias current to the input buffer based at least in part on a reference voltage. The biasing generation and distribution circuitry includes dynamic voltage bias circuitry that adjusts the bias current and reference voltage tracking circuitry that controls operation of the dynamic voltage bias circuitry based on the reference voltage.
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公开(公告)号：US20230223059A1
公开(公告)日：2023-07-13
申请号：US17575378
申请日：2022-01-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshiro Riho , Hiroshi Akamatsu , Jian Long , Kevin G. Werhane , Liang Liu , Yoshinori Fujiwara
IPC: G11C7/10
CPC classification number: G11C7/1087
Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.
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Patent Agency Ranking
公开(公告)号：US11727967B2
公开(公告)日：2023-08-15
申请号：US17575378
申请日：2022-01-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshiro Riho , Hiroshi Akamatsu , Jian Long , Kevin G. Werhane , Liang Liu , Yoshinori Fujiwara
IPC: G11C7/10
CPC classification number: G11C7/1087
Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.
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公开(公告)号：US20230024008A1
公开(公告)日：2023-01-26
申请号：US17937532
申请日：2022-10-03
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a fuse, a first driver circuit, and a second driver circuit. The fuse is configured to store a bit of information. The first driver circuit includes a first input terminal electrically connected to the fuse and a first output terminal electrically connected to a first latch input terminal. The second driver circuit includes a second input terminal electrically connected to the fuse and a second output terminal electrically connected to a second latch input terminal. The second latch input terminal is electrically isolated from the first latch input terminal by the first driver circuit and the second driver circuit.
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公开(公告)号：US11462283B2
公开(公告)日：2022-10-04
申请号：US17003363
申请日：2020-08-26
Applicant: Micron Technology, Inc.
Inventor： Liang Liu
Abstract: Latch circuits with improved single event upset immunity and related systems, apparatuses, and methods are disclosed. An apparatus includes a dual interlock storage cell (DICE) latch circuit including a first input node corresponding to a first path and a second input node corresponding to a second path. The first input node is electrically isolated from the second input node.
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公开(公告)号：US20220311335A1
公开(公告)日：2022-09-29
申请号：US17840434
申请日：2022-06-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
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公开(公告)号：US11374488B2
公开(公告)日：2022-06-28
申请号：US16321769
申请日：2018-12-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
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