中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

33 records (took 0.019 seconds)

    CACHE BYPASS
    1.
    发明公开
    CACHE BYPASS 审中-公开

    公开(公告)号：US20230418756A1

    公开(公告)日：2023-12-28

    申请号：US18215117

    申请日：2023-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Patrick Estep ,  Stephen S. Pawlowski ,  Nicola Del Gatto

    IPC: G06F12/0888 ,  G06F12/0804

    CPC classification number: G06F12/0888 ,  G06F12/0804

    Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

    INCREASING CACHE HITS FOR SYNTHETIC APERTURE RADAR
    3.
    发明申请
    INCREASING CACHE HITS FOR SYNTHETIC APERTURE RADAR 有权

    公开(公告)号：US20220317283A1

    公开(公告)日：2022-10-06

    申请号：US17240548

    申请日：2021-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Patrick Estep ,  Tony M. Brewer ,  Bryan Hornung ,  Douglas Vanesko

    IPC: G01S13/90 ,  G06F12/0815

    Abstract: A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.

    Increasing cache hits for synthetic aperture radar
    6.
    发明授权
    Increasing cache hits for synthetic aperture radar 有权

    公开(公告)号：US11802957B2

    公开(公告)日：2023-10-31

    申请号：US17240548

    申请日：2021-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Patrick Estep ,  Tony M. Brewer ,  Bryan Hornung ,  Douglas Vanesko

    IPC: G01S13/90 ,  G06F12/0815

    CPC classification number: G01S13/9021 ,  G01S13/9005 ,  G01S13/9056 ,  G06F12/0815 ,  G06F2212/1021

    Abstract: A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.

    Debugging dataflow computer architectures
    7.
    发明授权
    Debugging dataflow computer architectures 有权

    公开(公告)号：US11720475B2

    公开(公告)日：2023-08-08

    申请号：US17991390

    申请日：2022-11-21

    Applicant: Micron Technology, Inc.

    Inventor： Skyler Arron Windh ,  Tony M. Brewer ,  Patrick Estep

    IPC: G06F9/44 ,  G06F11/36 ,  G06F9/30

    CPC classification number: G06F11/3656 ,  G06F9/30189 ,  G06F11/3644 ,  G06F11/3664

    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

    MECHANISM TO TRIGGER EARLY TERMINATION OF COOPERATING PROCESSES
    8.
    发明申请
    MECHANISM TO TRIGGER EARLY TERMINATION OF COOPERATING PROCESSES 有权

    公开(公告)号：US20230074452A1

    公开(公告)日：2023-03-09

    申请号：US17984817

    申请日：2022-11-10

    Applicant: Micron Technology, Inc.

    Inventor： Patrick Estep ,  Skyler Arron Windh ,  Tony M. Brewer

    IPC: G06F9/54 ,  G06F9/30

    Abstract: Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

    CHAINED RESOURCE LOCKING
    9.
    发明申请
    CHAINED RESOURCE LOCKING 有权

    公开(公告)号：US20250094242A1

    公开(公告)日：2025-03-20

    申请号：US18959384

    申请日：2024-11-25

    Applicant: Micron Technology, Inc.

    Inventor： Patrick Estep ,  Tony M. Brewer

    IPC: G06F9/52 ,  G06F9/50

    Abstract: Devices and techniques for chained resource locking are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.

    MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
    10.
    发明申请
    MEMORY CONTROLLER FOR MANAGING RAID INFORMATION 有权

    公开(公告)号：US20240427526A1

    公开(公告)日：2024-12-26

    申请号：US18830096

    申请日：2024-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Emanuele Confalonieri ,  Paolo Amato ,  Patrick Estep ,  Stephen S. Pawlowski

    IPC: G06F3/06 ,  G06F12/0864

    Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Patent Agency Ranking