公开(公告)号：US11862215B2

公开(公告)日：2024-01-02

申请号：US17460042

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Sateesh Talasila ,  Chandrasekhar Mandalapu ,  Robert Douglas Cassel ,  Sundaravadivel Rajarajan ,  Iniyan Soundappa Elango ,  Srivatsan Venkatesan

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.

公开(公告)号：US20230069190A1

公开(公告)日：2023-03-02

申请号：US17460042

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Sateesh Talasila ,  Chandrasekhar Mandalapu ,  Robert Douglas Cassel ,  Sundaravadivel Rajarajan ,  Iniyan Soundappa Elango ,  Srivatsan Venkatesan

IPC: G11C13/00

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.