公开(公告)号：US20230025508A1

公开(公告)日：2023-01-26

申请号：US17492143

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Peng Fei ,  Yiran Liu ,  Shakeel Bukhari

IPC: G06F3/06

Abstract: A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.

公开(公告)号：US11934676B2

公开(公告)日：2024-03-19

申请号：US17492143

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Naveen Bolisetty ,  Peng Fei ,  Yiran Liu ,  Shakeel Bukhari

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.