公开(公告)号：US20240355397A1

公开(公告)日：2024-10-24

申请号：US18762228

申请日：2024-07-02

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi ,  Taehyun Kim ,  Theodore T. Pekny

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C16/3459

Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

公开(公告)号：US12057174B2

公开(公告)日：2024-08-06

申请号：US17669073

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi ,  Taehyun Kim ,  Theodore T. Pekny

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C16/3459

Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

公开(公告)号：US11443778B1

公开(公告)日：2022-09-13

申请号：US17224540

申请日：2021-04-07

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi

IPC: G11C5/14

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including: detecting that the charge pump has entered a recovery period; causing the oscillator to output, to the charge pump during a first time period of the recovery period, a first clock signal comprising a lower frequency than output during a time period preceding the recovery period; detecting that a voltage level from the level detector satisfies a trip point criterion; and causing the oscillator to output, to the charge pump during a second time period of the recovery period and responsive to the detecting, a second clock signal comprising a higher frequency than output during the time period preceding the recovery period.

公开(公告)号：US11763858B2

公开(公告)日：2023-09-19

申请号：US17890047

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.

公开(公告)号：US20230057289A1

公开(公告)日：2023-02-23

申请号：US17669073

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi ,  Taehyun Kim ,  Theodore T. Pekny

IPC: G11C11/4099 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/408

Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

公开(公告)号：US20220392498A1

公开(公告)日：2022-12-08

申请号：US17890047

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Vivek Venkata Kalluru ,  Michele Piccardi

IPC: G11C5/14

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.