-
公开(公告)号：US20250138781A1
公开(公告)日：2025-05-01
申请号：US18787854
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Xinyu Wu , Peter L. Brown , Troy A. Manning
Abstract: A processing unit can include an activation function unit. Data can be received at a plurality of registers of a processing unit of a memory sub-system. The data can be received at a multiply-accumulate (MAC) unit coupled to the plurality of registers. The first plurality of operations can be performed at the MAC unit to generate a first output. The first output can be provided to the activation function unit. The first output can be provided from the AFU to the plurality of registers utilizing a bus or a signal line that couples the plurality of registers to the AFU.
-
公开(公告)号：US11017878B1
公开(公告)日：2021-05-25
申请号：US16719911
申请日：2019-12-18
Applicant: Micron Technology, Inc.
Abstract: Methods, systems, and devices for memory device with a dynamic fuse array are described. Techniques and apparatus are described herein for storing an address of a set of the array of latches that is associated with a set of the array of fuses. A se of an array of fuses may include a first portion for indicating the value of the parameter and a second portion for indicating an address of a set of the array of latches that is to receive the parameter stored in the first portion. An enabled set of fuses may indicate that the block is storing a value of a parameter for operating the memory device. By storing the address for the set of the array latches in the set of the array of fuses, a memory device may have a dynamic mapping between the array of latches and the array of fuses. Such a dynamic mapping may reduce an area used by the array of fuses and may make some parameters modifiable.
-
Patent Agency Ranking
公开(公告)号：US20210158858A1
公开(公告)日：2021-05-27
申请号：US17133755
申请日：2020-12-24
Applicant: Micron Technology, Inc.
IPC: G11C11/4093 , G11C11/4074
Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
-
公开(公告)号：US11302386B2
公开(公告)日：2022-04-12
申请号：US17133755
申请日：2020-12-24
Applicant: Micron Technology, Inc.
IPC: G11C11/4093 , G11C11/4074
Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
-
公开(公告)号：US10892005B1
公开(公告)日：2021-01-12
申请号：US16696225
申请日：2019-11-26
Applicant: Micron Technology, Inc.
IPC: G11C11/4093 , G11C11/4074
Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
-
公开(公告)号：US20250068393A1
公开(公告)日：2025-02-27
申请号：US18771433
申请日：2024-07-12
Applicant: Micron Technology, Inc.
Inventor： Junxian Ding , Xinyu Wu
Abstract: A memory apparatus may include an array of memory cells, an adder, and control circuitry coupled to the array and to the adder. The control circuitry can cause data comprising a lookup table to be stored in the array, receive first signaling indicative of a first particular input to the machine learning model, and receive second signaling indicative of a second particular input to the machine learning model. The control circuitry can cause the first particular input to be indexed to a first particular result in the lookup table, cause the second particular input to be indexed to a second particular result in the lookup table, cause the adder to accumulate the first particular result and the second particular result into an output, and send third signaling indicative of the output.
-
7.发明公开公开(公告)号：US20240070801A1
公开(公告)日：2024-02-29
申请号：US17900018
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Xinyu Wu , Timothy Paul Finkbeiner , Peter Lawrence Brown , Troy Dale Larsen , Glen Earl Hush , Troy Allen Manning
CPC classification number: G06T1/60 , G06N3/063 , G06T7/10 , G06V10/82 , G06F12/023
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, an artificial intelligence system uses a memory device to provide inference results. Image data from a camera is provided to the memory device. The memory device stores the image data received from the camera. The memory device includes dynamic random access memory (DRAM), and static random access memory (SRAM). The memory device also includes a processor to run a neural network. The neural network uses the image data as input. An output from the neural network provides an inference result. In one example, the memory device has a same form factor as a conventional DRAM device. The memory device includes a multiply-accumulate (MAC) engine that supports computations for the neural network.
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
