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公开(公告)号：US10403330B1
公开(公告)日：2019-09-03
申请号：US16163720
申请日：2018-10-18
Applicant: Micron Technology, Inc.
Inventor： Harish N. Venkata , Yu-Feng Chen
Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.
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公开(公告)号：US20190198127A1
公开(公告)日：2019-06-27
申请号：US15851129
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Yu-Feng Chen , Scott E. Smith
CPC classification number: G11C17/16 , G11C7/1006 , G11C7/22 , G11C17/18 , G11C29/04 , G11C29/812
Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
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公开(公告)号：US20190172546A1
公开(公告)日：2019-06-06
申请号：US15830281
申请日：2017-12-04
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , John E. Riley , Yu-Feng Chen
Abstract: A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
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公开(公告)号：US10360989B2
公开(公告)日：2019-07-23
申请号：US15830281
申请日：2017-12-04
Applicant: Micron Technology, Inc.
Inventor： Raghukiran Sreeramaneni , John E. Riley , Yu-Feng Chen
Abstract: A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
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公开(公告)号：US10672489B2
公开(公告)日：2020-06-02
申请号：US16446848
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Girish N. Cherussery , Scott E. Smith , Yu-Feng Chen
Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.
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Patent Agency Ranking
公开(公告)号：US20190392887A1
公开(公告)日：2019-12-26
申请号：US16556763
申请日：2019-08-30
Applicant: Micron Technology, Inc.
Inventor： Yu-Feng Chen , Byung S. Moon , Myung Ho Bae , Harish N. Venkata
IPC: G11C11/4074 , G11C11/408 , G06F13/42
Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
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公开(公告)号：US10373698B1
公开(公告)日：2019-08-06
申请号：US15967022
申请日：2018-04-30
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Girish N. Cherussery , Scott E. Smith , Yu-Feng Chen
Abstract: An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.
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公开(公告)号：US10332609B1
公开(公告)日：2019-06-25
申请号：US15851129
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Yu-Feng Chen , Scott E. Smith
CPC classification number: G11C17/16 , G11C7/1006 , G11C7/22 , G11C17/18 , G11C29/04 , G11C29/812
Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
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公开(公告)号：US11087820B2
公开(公告)日：2021-08-10
申请号：US16556763
申请日：2019-08-30
Applicant: Micron Technology, Inc.
Inventor： Yu-Feng Chen , Byung S. Moon , Myung Ho Bae , Harish N. Venkata
IPC: G11C11/4074 , G11C11/408 , G06F13/42 , G11C11/4094 , G11C8/12
Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
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公开(公告)号：US20190333594A1
公开(公告)日：2019-10-31
申请号：US16446848
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Girish N. Cherussery , Scott E. Smith , Yu-Feng Chen
IPC: G11C17/16 , G11C29/00 , G11C7/10 , H01L23/525 , G11C11/34
Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.
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