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公开(公告)号：US20210280267A1
公开(公告)日：2021-09-09
申请号：US16811691
申请日：2020-03-06
Applicant: Micron Technology, Inc.
Inventor： Gary Howe , John E. Riley
Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.
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公开(公告)号：US10373698B1
公开(公告)日：2019-08-06
申请号：US15967022
申请日：2018-04-30
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Girish N. Cherussery , Scott E. Smith , Yu-Feng Chen
Abstract: An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.
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公开(公告)号：US10332609B1
公开(公告)日：2019-06-25
申请号：US15851129
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Yu-Feng Chen , Scott E. Smith
CPC classification number: G11C17/16 , G11C7/1006 , G11C7/22 , G11C17/18 , G11C29/04 , G11C29/812
Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
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公开(公告)号：US12165690B2
公开(公告)日：2024-12-10
申请号：US17849100
申请日：2022-06-24
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Joo-Sang Lee , Scott E. Smith
IPC: G11C11/406 , G11C11/4074
Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.
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公开(公告)号：US20230395183A1
公开(公告)日：2023-12-07
申请号：US17889369
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Matthew Young , John E. Riley
CPC classification number: G11C29/52 , G11C29/789 , G11C7/1039
Abstract: The present disclosure includes apparatus, methods, and systems for error detection for a semiconductor device. An apparatus includes a memory array, a detector array, and a detector coupled to the detector array. The detector is configured to detect an error in a portion of the detector array and output an output signal to memory components coupled to the detector array in response to detecting the error.
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Patent Agency Ranking
公开(公告)号：US20200098398A1
公开(公告)日：2020-03-26
申请号：US16143105
申请日：2018-09-26
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , John E. Riley
Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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公开(公告)号：US20190333594A1
公开(公告)日：2019-10-31
申请号：US16446848
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Girish N. Cherussery , Scott E. Smith , Yu-Feng Chen
IPC: G11C17/16 , G11C29/00 , G11C7/10 , H01L23/525 , G11C11/34
Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.
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公开(公告)号：US10403390B1
公开(公告)日：2019-09-03
申请号：US15948585
申请日：2018-04-09
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , John E. Riley
Abstract: Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.
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公开(公告)号：US11984189B2
公开(公告)日：2024-05-14
申请号：US17205705
申请日：2021-03-18
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , John E. Riley
Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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公开(公告)号：US20230307033A1
公开(公告)日：2023-09-28
申请号：US17701950
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Scott E. Smith , Jennifer E. Taylor , Gary L. Howe
IPC: G06F3/06 , G11C11/4096 , G11C11/4076
CPC classification number: G06F3/061 , G11C11/4096 , G11C11/4076 , G06F3/0653 , G06F3/0656 , G06F3/0673
Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.
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