公开(公告)号：US20210227361A1

公开(公告)日：2021-07-22

申请号：US17204522

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: H04W4/33 ,  H04L29/12 ,  H04W4/02 ,  H04B17/318 ,  H04W4/029 ,  H04B17/26 ,  H04B17/27

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11016885B2

公开(公告)日：2021-05-25

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/06 ,  G06F12/04 ,  G06F9/30

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11928055B2

公开(公告)日：2024-03-12

申请号：US17975164

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/02 ,  H04W4/029 ,  H04W4/33 ,  G06F9/30 ,  H04B17/24 ,  H04L101/622 ,  H04L101/69 ,  H04W84/12

CPC classification number: G06F12/0607 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/026 ,  H04W4/029 ,  H04W4/33 ,  G06F9/30134 ,  H04B17/24 ,  H04L2101/622 ,  H04L2101/69 ,  H04W84/12

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20200272562A1

公开(公告)日：2020-08-27

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20230053291A1

公开(公告)日：2023-02-16

申请号：US17975164

申请日：2022-10-27

Applicant: Micron Technology. Inc/

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US11507504B2

公开(公告)日：2022-11-22

申请号：US17204522

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F12/06 ,  G06F12/04 ,  H04B17/26 ,  H04B17/27 ,  H04B17/318 ,  H04W4/33 ,  H04W4/029 ,  H04W4/02 ,  G06F9/30 ,  H04B17/24 ,  H04W84/12 ,  H04L101/622 ,  H04L101/69

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.