公开(公告)号：US06279077B1

公开(公告)日：2001-08-21

申请号：US08821874

申请日：1997-03-21

申请人： Mitra Nasserbakht ,  Patrick W. Bosshart

发明人： Mitra Nasserbakht ,  Patrick W. Bosshart

IPC分类号： G06F1208

CPC分类号： G06F12/0859 ,  G06F12/0804

摘要： A microprocessor (5) including a plurality of write buffers (30) of varying sizes is disclosed. The varying sizes of the write buffers (30) allow for each write transaction from the core of the microprocessor (5) to be assigned to the most efficient write buffer size. Each write buffer (30) also includes sequential control logic (50) that issues a status code indicating the extent to which its write buffer (30) is filled; the control logic (50) advances to a more full state responsive to receiving a new data transaction from the internal bus, and advances to a more empty state responsive to completing a write transaction to the external bus. Each write buffer (30) communicates data from an internal bus (PBUS) to an external bus (BBUS) in a manner that is synchronized in the control path, rather than in the data path. Clock domain translation circuitry (65) is included within timing control circuitry (62) to translate the control signal from one clock domain to another, thus ensuring that overlapping writes do not occur. Internal snoop control circuitry (71) is also provided, for controlling access to the write buffers (30) so that memory reads missing in on-chip cache may be performed to the write buffers (30), rather than to main memory (21), if the data remains resident therein. A read buffer (33) is also disclosed, and has a plurality of entries for receiving blocks of data from the external bus (BBUS); upon receipt of a block of data, the read buffer (33) indicates the presence of data therein to the core of the microprocessor (5) to initiate its retrieval for execution of an instruction.

摘要翻译： 公开了一种包括多个不同大小的写入缓冲器（30）的微处理器（5）。 写入缓冲器（30）的不同大小允许将来自微处理器（5）的核心的每个写事务分配给最有效的写入缓冲器大小。 每个写缓冲器（30）还包括顺序控制逻辑（50），其发出指示其写缓冲器（30）被填充的程度的状态码; 所述控制逻辑（50）响应于从所述内部总线接收到新的数据事务而进入更全状态，并且响应于完成对所述外部总线的写入事务而进入更空的状态。 每个写入缓冲器（30）以在控制路径中而不是数据路径中同步的方式将数据从内部总线（PBUS）传送到外部总线（BBUS）。 时钟域转换电路（65）包括在定时控制电路（62）内，以将控制信号从一个时钟域转换到另一个时钟域，从而确保不发生重叠写入。 还提供了内部窥探控制电路（71），用于控制对写入缓冲器（30）的访问，使得可以对写入缓冲器（30）而不是主存储器（21）执行片上高速缓存中缺少的存储器读取， 如果数据保留在其中。 还公开了读缓冲器（33），并且具有用于从外部总线（BBUS）接收数据块的多个条目; 读取缓冲器（33）在接收到数据块之后，指示其中的数据存在于微处理器（5）的核心以启动其检索以执行指令。

公开(公告)号：US08495020B1

公开(公告)日：2013-07-23

申请号：US12163973

申请日：2008-06-27

申请人： Gitty N Nasserbakht ,  Mitra Nasserbakht

发明人： Gitty N Nasserbakht ,  Mitra Nasserbakht

IPC分类号： G06F17/30

CPC分类号： G06F17/30864 ,  G06F15/7807 ,  G06F17/30011 ,  G06F17/30038 ,  G06F17/30076 ,  G06F17/30699 ,  G06Q10/1093 ,  G06Q30/0261 ,  H04M1/72522 ,  H04M1/72527 ,  H04W4/025 ,  H04W4/60 ,  Y02D10/12 ,  Y02D10/13

摘要： A time-based intelligence system provides robust storage, access, and processing of information on a mobile device. An automated mobile assistant system provides automated, proactive and anticipatory services for the user of the system. In an example, a customizable personal mobile device for communication and organization can include a core engine and a plurality of modules coupled to the core engine to perform a different one of a plurality of classes of functionality of the mobile device, where each said module includes a processing element and memory dedicated for use by said module.

摘要翻译： 基于时间的智能系统提供对移动设备上信息的强大的存储，访问和处理。 自动化移动助理系统为系统的用户提供自动化，主动和预期的服务。 在一个示例中，用于通信和组织的可定制的个人移动设备可以包括核心引擎和耦合到核心引擎的多个模块以执行移动设备的多个功能类别中的不同的一个，其中每个所述模块包括 专用于所述模块的处理元件和存储器。

公开(公告)号：US08326353B1

公开(公告)日：2012-12-04

申请号：US12163878

申请日：2008-06-27

申请人： Gitty N Nasserbakht ,  Mitra Nasserbakht

发明人： Gitty N Nasserbakht ,  Mitra Nasserbakht

IPC分类号： H04M1/00

CPC分类号： G06F17/30864 ,  G06F15/7807 ,  G06F17/30011 ,  G06F17/30038 ,  G06F17/30076 ,  G06F17/30699 ,  G06Q10/1093 ,  G06Q30/0261 ,  H04M1/72522 ,  H04M1/72527 ,  H04W4/025 ,  H04W4/60 ,  Y02D10/12 ,  Y02D10/13

摘要： A customized personal mobile device for communication and organization comprises a core engine and a plurality of modules coupled to the core engine. Each of the modules is dedicated to perform a different one of a plurality of classes of functionality of the mobile device, where each said module includes a processing element and memory dedicated for use by said module. A time-based intelligence system provides robust storage, access, and processing of information on a mobile device.

摘要翻译： 用于通信和组织的定制的个人移动设备包括核心引擎和耦合到核心引擎的多个模块。 每个模块专用于执行移动设备的多个功能类别中的不同类别，其中每个所述模块包括专用于所述模块的处理元件和存储器。 基于时间的智能系统提供对移动设备上信息的强大的存储，访问和处理。

公开(公告)号：US08311513B1

公开(公告)日：2012-11-13

申请号：US12193711

申请日：2008-08-18

申请人： Gitty N Nasserbakht ,  Mitra Nasserbakht

发明人： Gitty N Nasserbakht ,  Mitra Nasserbakht

IPC分类号： H04M3/16

CPC分类号： H04L63/08 ,  G06F1/1647 ,  G06F1/1654 ,  G06F1/3218 ,  G06F21/554 ,  G06F21/6218 ,  G06F2221/2111 ,  G06F2221/2143 ,  G06Q10/109 ,  G06Q30/0261 ,  G06Q30/0267 ,  H04L51/00 ,  H04L63/10 ,  H04M1/72566 ,  H04W12/06

摘要： An automated mobile assistant system provides automated, proactive and anticipatory services for the user of the system. A scheduling system for a mobile device is described and can include a memory to store calendar events and a scheduler to automatically organize the events based on at least one of temporal, geographical, contextual availability, user-preference, past activities, usage pattern, proximity to other users or events, or combinations thereof. In an example, a customizable personal mobile device for communication and organization can include a core engine and a plurality of modules coupled to the core engine to perform a different one of a plurality of classes of functionality of the mobile device, where each said module includes a processing element and memory dedicated for use by said module. A time-based intelligence system provides robust storage, access, and processing of information on a mobile device.

摘要翻译： 自动化移动助理系统为系统的用户提供自动化，主动和预期的服务。 描述了用于移动设备的调度系统，并且可以包括用于存储日历事件的存储器和调度器，以基于时间，地理，上下文可用性，用户偏好，过去活动，使用模式，接近度中的至少一个来自动组织事件 到其他用户或事件，或其组合。 在一个示例中，用于通信和组织的可定制的个人移动设备可以包括核心引擎和耦合到核心引擎的多个模块以执行移动设备的多个功能类别中的不同的一个，其中每个所述模块包括 专用于所述模块的处理元件和存储器。 基于时间的智能系统提供对移动设备上信息的强大的存储，访问和处理。

公开(公告)号：US5796995A

公开(公告)日：1998-08-18

申请号：US810175

申请日：1997-02-28

申请人： Mitra Nasserbakht ,  Patrick W. Bosshart

发明人： Mitra Nasserbakht ,  Patrick W. Bosshart

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at different multiples of a system clock signal. The clock generation circuitry (20) includes a counter (60) that indicates, for a given frequency ratio, signals (REGION) indicating the current phase region of the faster clock (PCLK) relative to the slower clock (BCLK). The clock domain translation circuit (50a) includes a series of input registers (82, 84) in sequence, with the output of each as well as the input signal line (IN PCLK) coupled to inputs of a multiplexer (80). The multiplexer (80) selects either the input signal directly or the output of one of the registers for application to an output register (90), clocked by the slower clock signal (BCLK), depending upon the phase region of the faster clock (PCLK) relative to the slower clock (BCLK) for communication of that signal. As a result, the input digital signal is held for enough time to be properly clocked in, depending upon the phase region, thus enabling frequency ratios of non-integer values to be utilized in system operation.

摘要翻译： 公开了一种包括用于将数字信号从高速时钟域传送到低速时钟域的时钟域转换电路（50a）的微处理器（5）。 所公开的微处理器（5）包括产生系统时钟信号的不同倍数的内部和总线时钟的时钟产生电路（20）。 时钟产生电路（20）包括计数器（60），对于给定的频率比率，指示相对于较慢时钟（BCLK）指示较快时钟（PCLK）的当前相位区域的信号（REGION）。 时钟域转换电路（50a）依次包括一系列输入寄存器（82,84），其中每个的输出以及耦合到多路复用器输入端的输入信号线（IN + E，uns + EE PCLK） （80）。 多路复用器（80）根据较快时钟的相位区域（PCLK）选择直接输入信号或其中一个寄存器的输出以供应给由较慢时钟信号（BCLK）计时的输出寄存器（90） ）相对于较慢时钟（BCLK），用于通信该信号。 结果，根据相位区域，输入数字信号被保持足够的时间以适当地计时，从而使得可以在系统操作中使用非整数值的频率比。

公开(公告)号：US06122703A

公开(公告)日：2000-09-19

申请号：US912913

申请日：1997-08-15

申请人： Mitra Nasserbakht

发明人： Mitra Nasserbakht

IPC分类号： G06F17/14 ,  G06F12/00

CPC分类号： G06F17/142

摘要： Improved Fourier transform processing systems for a data transmission system are disclosed. The improved Fourier transform processing systems efficiently performs Fourier transform signal processing. In addition, the improved Fourier transform processing can perform address transformations to better and more efficiently use a memory system for in-place processing. The address transformations are provided by a generalized address translation algorithm that works for any size Fourier transform, in any radix, and with various memory architectures. The processing system can also be pipelined. The invention is particularly well suited for performing in-place processing in a data transmission system.

公开(公告)号：US06401162B1

公开(公告)日：2002-06-04

申请号：US09547956

申请日：2000-04-12

申请人： Mitra Nasserbakht

发明人： Mitra Nasserbakht

IPC分类号： G06F1200

CPC分类号： G06F17/142

摘要： Improved Fourier transform processing systems for a data transmission system are disclosed. The improved Fourier transform processing systems efficiently performs Fourier transform signal processing. In addition, the improved Fourier transform processing can perform address transformations to better and more efficiently use a memory system for in-place processing. The address transformations are provided by a generalized address translation algorithm that works for any size Fourier transform, in any radix, and with various memory architectures. The processing system can also be pipelined. The invention is particularly well suited for performing in-place processing in a data transmission system.

摘要翻译： 公开了一种用于数据传输系统的改进的傅里叶变换处理系统。 改进的傅里叶变换处理系统有效执行傅里叶变换信号处理。 另外，改进的傅里叶变换处理可以执行地址转换以更好地和更有效地使用存储器系统进行就地处理。 地址转换由通用地址转换算法提供，该算法适用于任何大小的傅里叶变换，任何基数以及各种存储器体系结构。 处理系统也可以流水线化。 本发明特别适用于在数据传输系统中执行就地处理。

公开(公告)号：US5809514A

公开(公告)日：1998-09-15

申请号：US805821

申请日：1997-02-26

申请人： Mitra Nasserbakht ,  Uming Ko

发明人： Mitra Nasserbakht ,  Uming Ko

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0879

摘要： The present invention provides a method for transferring groups of data between a microprocessor cache memory (114) and an external memory (105) across a data bus (Bbus). Each group of data includes as many bits of data as the width of the bus (Bubs) with the total amount of data transferred filling a line in the cache memory (114). The bus interface unit (112) of the microprocessor (110) initiates a burst read by starting a read request, asserting the address strobe bit and sending the initial requested address on the external bus address bits of the microprocessor (110). The external system will then respond by asserting a burst ready signal, followed by the data bits residing in the appropriate address position. The particular addresses for this data is selected according to the current burst mode, which may be high performance, low power or compatible with a previously known burst mode. Subsequent groups of data are then sent in subsequent cycles according to the prescribed order of the burst mode up to n (=B/b) transfers. In a high performance mode the first group of bytes requested are always returned first. The next transfer will supply the necessary data that will satisfy the next level of data size hierarchy. Thereafter, transfer order follows an increasing wrap-around order. A low power mode includes an initial data order similar to the high performance mode with the additional limitation that only one address bit changes for each sequential data group. A burst write is performed similarly.

摘要翻译： 本发明提供一种用于在数据总线（Bbus）之间的微处理器高速缓冲存储器（114）和外部存储器（105）之间传送数据组的方法。 每组数据包括与总线的宽度（Bub）一样多的数据位，其中传输的数据总量填充在高速缓存存储器（114）中。 微处理器（110）的总线接口单元（112）通过启动读取请求来启动脉冲串读取，断言地址选通位，并在微处理器（110）的外部总线地址位上发送初始请求的地址。 然后，外部系统将通过断言突发就绪信号进行响应，接着是位于适当地址位置的数据位。 根据当前突发模式选择该数据的特定地址，其可以是高性能，低功率或与先前已知的突发模式兼容。 然后根据突发模式的规定顺序在随后的周期内发送后续的数据组，直到n（= B / b）个传输。 在高性能模式下，请求的第一组字节始终返回。 下一次传输将提供满足下一级数据大小层级的必要数据。 此后，转移订单遵循递增的环绕顺序。 低功率模式包括类似于高性能模式的初始数据顺序，附加限制是每个顺序数据组只有一个地址位改变。 突发写入类似地执行。

公开(公告)号：US5534793A

公开(公告)日：1996-07-09

申请号：US378036

申请日：1995-01-24

申请人： Mitra Nasserbakht

发明人： Mitra Nasserbakht

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17704

摘要： The parallel antifuse scheme may be applied to a field programmable gate array architecture (10) having a logic module (16) with an output coupled to an output track (34, 54, 114, 144, 178, 198) coupled via a cross antifuse (38, 58, 116, 184, 208) to an connecting track (36, 56, 64, 118, 154, 182, 205, 206). The connecting track is further coupled via at least one cross antifuse (44, 46, 72, 74, 120, 122, 160, 162, 190, 218, 220) to at least one input track (40, 42, 68, 70, 188, 214, 216) coupled to an input of at least one logic module. The circuit includes a compensation track (124, 150, 180, 200) running generally in parallel with the output track and at least one parallel antifuse (125, 158, 186, 212) programmably coupling the compensation track (124, 150, 180, 200) and the connecting track. One or more controllable switch (130, 152, 174, 176, 194, 196), such as a pass transistor, is coupled between the output track and the compensation track.

摘要翻译： 并联反熔丝方案可以应用于具有逻辑模块（16）的现场可编程门阵列架构（10），其中输出耦合到通过交叉反熔丝耦合的输出轨道（34,54,114,144,178,198） （38,58,116,184,208）连接到连接轨道（36,56,64,118,154,182,205,206）。 连接轨道还经由至少一个交叉反熔丝（44,46,72,74,120,122,160,162,190,218,220）耦合到至少一个输入轨道（40,42,68,70， 188,214,216），耦合到至少一个逻辑模块的输入。 电路包括通常与输出轨道平行运行的补偿轨道（124,150,180,200）和至少一个平行反熔丝（125,158,186,212），可编程地将补偿轨道（124,150,180,200） 200）和连接轨道。 一个或多个可控开关（130,152,174,176,194,196），例如传输晶体管，耦合在输出轨道和补偿轨道之间。

公开(公告)号：US5491431A

公开(公告)日：1996-02-13

申请号：US318322

申请日：1994-10-05

申请人： Mitra Nasserbakht

发明人： Mitra Nasserbakht

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A logic module for use in gate arrays and the like includes five two input multiplexers 50, 52, 54, 56, 58. The module includes 10 data input terminals I1, I2, I3, I4, I5, I6, I7, I8, I9, I10. The first input terminals I1, I2 are connected to the data input terminals of multiplexer 50. Inputs I3, I4 and I5 are connected respectively to the select, the first data and second data inputs to multiplexer 52. Inputs I6, I7 are connected to the data inputs of multiplexer 54. Inputs I8, I9, I10 are connected to the first data, second data and select inputs to multiplexer 56. The output of multiplexer 52 is connected to the select input to multiplexers 50 and 54. The output of multiplexer 56 is connected to the select input to multiplexer 58 while the outputs of multiplexers 50 and 54 are respectively connected to the first and second data input to multiplexer 58. The output of multiplexer 58 comprises the logic circuit output O.

摘要翻译： 用于门阵列等的逻辑模块包括五个两个输入多路复用器50,52,54,56,58。该模块包括10个数据输入端I1，I2，I3，I4，I5，I6，I7，I8，I9 ，I10。 第一输入端I1，I2连接到多路复用器50的数据输入端。输入I3，I4和I5分别连接到选择，第一数据和第二数据输入到多路复用器52.输入I6，I7连接到 输入I8，I9，I10连接到第一数据，第二数据和选择输入到多路复用器56.多路复用器52的输出连接到多路复用器50和54的选择输入。复用器56的输出 连接到选择输入到多路复用器58，而多路复用器50和54的输出分别连接到输入到复用器58的第一和第二数据。多路复用器58的输出包括逻辑电路输出O.