公开(公告)号：US20230207651A1

公开(公告)日：2023-06-29

申请号：US17561686

申请日：2021-12-23

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/0673

摘要： Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

公开(公告)号：US20230197855A1

公开(公告)日：2023-06-22

申请号：US17557995

申请日：2021-12-21

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/78618 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

公开(公告)号：US20230197816A1

公开(公告)日：2023-06-22

申请号：US17558061

申请日：2021-12-21

申请人： Mohammad HASAN ,  Mohit K. HARAN ,  Tahir GHANI ,  Anand S. MURTHY ,  Rushabh SHAH

发明人： Mohammad HASAN ,  Mohit K. HARAN ,  Tahir GHANI ,  Anand S. MURTHY ,  Rushabh SHAH

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

摘要： Integrated circuit structures having metal gate plug landed on dielectric anchor, and methods of fabricating integrated circuit structures having metal gate plug landed on dielectric anchor, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires, the dielectric structure having a bottommost surface below an uppermost surface of the STI structure. A dielectric gate plug is on the dielectric structure.