公开(公告)号：US10355121B2

公开(公告)日：2019-07-16

申请号：US15727592

申请日：2017-10-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  G11C16/02 ,  H01L27/115 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  H01L27/24 ,  G11C11/412 ,  G11C16/04

Abstract: A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.

公开(公告)号：US20170062600A1

公开(公告)日：2017-03-02

申请号：US15351389

申请日：2016-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  H01L27/115 ,  H01L27/24 ,  H01L27/11 ,  H01L27/108

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.

Abstract translation: 一种基于3D IC的系统，该系统包括：第一层，包括包括第一晶体管的第一存储单元，其中第一晶体管包括第一晶体管沟道; 覆盖第一层的第二层，第二层包括包括第二晶体管的第二存储单元，其中第二晶体管包括第二晶体管沟道，其中第二层包括垂直取向的掺杂区域，其中第二层包括至少一个至第二层通孔 具有小于400nm的直径，并且其中第一晶体管沟道和至少一个第二晶体管沟道中的至少一个直接耦合到垂直取向的掺杂区域中的至少一个。

公开(公告)号：US20180033881A1

公开(公告)日：2018-02-01

申请号：US15727592

申请日：2017-10-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  G11C11/4097 ,  H01L27/24 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  G11C11/404 ,  G11C16/02

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A semiconductor device, the device including: a first stratum including memory periphery circuits; a second stratum including an array of first memory cells, where the first stratum is overlaid by the second stratum; a third stratum including an array of second memory cells, where the second stratum is overlaid by the third stratum, where the first memory cells include a plurality of first polysilicon structures and the second memory cells include a plurality of second polysilicon structures, and where at least one of the first memory cells is self-aligned to at least one of the second memory cells.

公开(公告)号：US09496271B2

公开(公告)日：2016-11-15

申请号：US14506160

申请日：2014-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L27/115 ,  G11C16/02 ,  H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Abstract translation: 一种基于3D IC的系统，包括：包括第一晶体管的第一层; 覆盖第一层的第二层，第二层包括多个第二晶体管，其中第二层包括直径小于400nm的至少一个至第二层，并且其中多个第二晶体管中的至少一个 形成包括背偏置区域的两个稳定状态存储单元。

公开(公告)号：US09799761B2

公开(公告)日：2017-10-24

申请号：US15351389

申请日：2016-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  G11C16/02 ,  H01L27/115 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  H01L27/24 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.

公开(公告)号：US20150054090A1

公开(公告)日：2015-02-26

申请号：US14506160

申请日：2014-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Abstract translation: 一种基于3D IC的系统，包括：包括第一晶体管的第一层; 覆盖第一层的第二层，第二层包括多个第二晶体管，其中第二层包括直径小于400nm的至少一个至第二层，并且其中多个第二晶体管中的至少一个 形成包括背偏置区域的两个稳定状态存储单元。

公开(公告)号：US08902663B1

公开(公告)日：2014-12-02

申请号：US13792202

申请日：2013-03-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: G11C16/04 ,  G11C16/02

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A method of maintaining a memory state of a 3D memory, wherein the memory includes at least a first cell and a second cell overlying the first cell, the method including: applying a back-bias to the first cell and the second cell without interrupting data access to the memory, and generating at least two stable floating body charge levels of the memory state.

Abstract translation: 一种保持3D存储器的存储状态的方法，其中所述存储器至少包括第一单元和覆盖所述第一单元的第二单元，所述方法包括：将第一单元和所述第二单元的反向偏压应用于中断数据 访问存储器，并且产生存储器状态的至少两个稳定的浮动体电荷电平。