公开(公告)号：US10163465B1

公开(公告)日：2018-12-25

申请号：US15680216

申请日：2017-08-18

Applicant: NOVATEK Microelectronics Corp.

Inventor： Po-Yao Ko ,  Chien-Chung Chen ,  Hsu-Yu Huang ,  Chun-Po Huang

IPC: G11C8/10 ,  G11C7/10 ,  H03F3/30

Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.