公开(公告)号：US09537489B1

公开(公告)日：2017-01-03

申请号：US15135530

申请日：2016-04-21

Applicant: NOVATEK Microelectronics Corp.

Inventor： Po-Yao Ko

IPC: H03L5/00 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356182

Abstract: A level shifter for converting a first voltage range to a second voltage range includes a latch circuit, a stack device and a dynamic bias circuit. The latch circuit is used for outputting the second voltage range. The stack device, coupled to the latch circuit, includes a stack transistor, which is used for sustaining the second voltage range of the latch circuit. The dynamic bias circuit, coupled to the stack device, is used for turning on the stack transistor to toggle the latch circuit.

Abstract translation: 用于将第一电压范围转换为第二电压范围的电平移位器包括锁存电路，堆叠装置和动态偏置电路。 锁存电路用于输出第二电压范围。 耦合到锁存电路的堆叠装置包括用于维持锁存电路的第二电压范围的堆叠晶体管。 耦合到堆叠装置的动态偏置电路用于接通堆叠晶体管以切换锁存电路。

公开(公告)号：US10163465B1

公开(公告)日：2018-12-25

申请号：US15680216

申请日：2017-08-18

Applicant: NOVATEK Microelectronics Corp.

Inventor： Po-Yao Ko ,  Chien-Chung Chen ,  Hsu-Yu Huang ,  Chun-Po Huang

IPC: G11C8/10 ,  G11C7/10 ,  H03F3/30

Abstract: A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.

公开(公告)号：US20180302073A1

公开(公告)日：2018-10-18

申请号：US15488545

申请日：2017-04-17

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Po-Yao Ko ,  Yi-Ming Wu

IPC: H03K5/156 ,  H03K5/05 ,  H03K5/00

Abstract: A duty cycle calibration circuit and a frequency synthesizer using the same are provided. The duty cycle calibration circuit includes a single-ended correction circuit and a single-ended detection circuit. The single-ended correction circuit is configured to adjust a duty cycle of an input clock signal. The single-ended correction circuit includes a first slew rate controller, a second slew rate controller, and at least one logic gate. The first slew rate controller adjusts a rising slew rate of an output clock signal in response to a control signal. The second slew rate controller adjusts a falling slew rate of the output clock signal in response to the control signal. The single-ended detection circuit is configured to detect a duty cycle of the output clock signal by converting the duty cycle of the output clock signal to an average voltage to be served as the control signal.

公开(公告)号：US09825613B1

公开(公告)日：2017-11-21

申请号：US15585174

申请日：2017-05-03

Applicant: NOVATEK Microelectronics Corp.

Inventor： Po-Yao Ko

IPC: H03K19/00 ,  H03H11/30 ,  H03K17/00 ,  H03K5/24

CPC classification number: H03K5/24 ,  G01R35/005

Abstract: A resistor calibration system includes a reference resistor, a first control circuit, a second control circuit, a comparator, a multiplexer and a de-multiplexer. The first control circuit calibrates a first resistor and a duplicated first resistor. The second control circuit calibrates a second resistor. The comparator includes a first input terminal receiving a reference voltage, a second input terminal and an output terminal. The multiplexer includes a first input terminal coupled to the reference resistor and the first resistor, a second input terminal coupled to the duplicated first resistor and the second resistor, and an output terminal coupled to the second input terminal of the comparator. The de-multiplexer includes an input terminal coupled to the output terminal of the comparator, a first output terminal coupled to the first control circuit, and a second output terminal coupled to the second control circuit.