公开(公告)号：US11424741B2

公开(公告)日：2022-08-23

申请号：US17039921

申请日：2020-09-30

Applicant: NXP B.V.

Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

IPC: H03K17/687 ,  H03K17/567

Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

公开(公告)号：US11437981B1

公开(公告)日：2022-09-06

申请号：US17218400

申请日：2021-03-31

Applicant: NXP B.V.

Inventor： Domenico Liberti ,  Neil Edward Birns ,  Andre Gunther ,  Rob Cosaro

IPC: H03K3/03 ,  H03K3/011

Abstract: A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.

公开(公告)号：US20220103170A1

公开(公告)日：2022-03-31

申请号：US17039921

申请日：2020-09-30

Applicant: NXP B.V.

Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

IPC: H03K17/687 ,  H03K17/567

Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

公开(公告)号：US11295787B1

公开(公告)日：2022-04-05

申请号：US17134765

申请日：2020-12-28

Applicant: NXP B.V.

Inventor： Andre Gunther ,  Gerard Villar Pique ,  Avin Kurup ,  Domenico Liberti

IPC: G11C5/14 ,  H02M1/00 ,  H02H7/12

Abstract: A methodology and apparatus are disclosed for providing standby power during standby mode by applying a low frequency sampling clock signal to first and second comparators which are connected to compare an output voltage generated at an external capacitor to, respectively, a first higher voltage threshold and a second lower voltage threshold, where the first comparator generates an enable signal in response to the output voltage reaching the first higher voltage threshold for use in activating one or more switched regulator circuits to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold, and where the second comparator generates an undervoltage signal in response to the output voltage reaching the second lower voltage threshold for use in reactivating the main regulator to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold.

公开(公告)号：US11073857B1

公开(公告)日：2021-07-27

申请号：US17039926

申请日：2020-09-30

Applicant: NXP B.V.

Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

IPC: H03K19/0185 ,  G05F1/575 ,  H03F3/45 ,  H03K19/20 ,  H03K17/687

Abstract: A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.