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    Preserving a decoupling capacitor's charge during low power operation of a logic circuit
    1.
    发明授权
    Preserving a decoupling capacitor's charge during low power operation of a logic circuit 有权

    公开(公告)号：US12099394B2

    公开(公告)日：2024-09-24

    申请号：US17805652

    申请日：2022-06-06

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

    IPC: G06F1/32 ,  G06F1/3212 ,  G06F1/3296

    CPC classification number: G06F1/3212 ,  G06F1/3296

    Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

    Active N-well switching circuit for power switches
    2.
    发明授权
    Active N-well switching circuit for power switches 有权

    公开(公告)号：US11424741B2

    公开(公告)日：2022-08-23

    申请号：US17039921

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K17/687 ,  H03K17/567

    Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

    PRESERVING A DECOUPLING CAPACITOR'S CHARGE DURING LOW POWER OPERATION OF A LOGIC CIRCUIT
    3.
    发明公开
    PRESERVING A DECOUPLING CAPACITOR'S CHARGE DURING LOW POWER OPERATION OF A LOGIC CIRCUIT 审中-公开

    公开(公告)号：US20230393639A1

    公开(公告)日：2023-12-07

    申请号：US17805652

    申请日：2022-06-06

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

    IPC: G06F1/3212 ,  G06F1/3296

    CPC classification number: G06F1/3212 ,  G06F1/3296

    Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

    Reducing SRAM leakage using scalable switched capacitor regulators
    4.
    发明授权
    Reducing SRAM leakage using scalable switched capacitor regulators 有权

    公开(公告)号：US11295787B1

    公开(公告)日：2022-04-05

    申请号：US17134765

    申请日：2020-12-28

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Gerard Villar Pique ,  Avin Kurup ,  Domenico Liberti

    IPC: G11C5/14 ,  H02M1/00 ,  H02H7/12

    Abstract: A methodology and apparatus are disclosed for providing standby power during standby mode by applying a low frequency sampling clock signal to first and second comparators which are connected to compare an output voltage generated at an external capacitor to, respectively, a first higher voltage threshold and a second lower voltage threshold, where the first comparator generates an enable signal in response to the output voltage reaching the first higher voltage threshold for use in activating one or more switched regulator circuits to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold, and where the second comparator generates an undervoltage signal in response to the output voltage reaching the second lower voltage threshold for use in reactivating the main regulator to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold.

    Maximum voltage selector for power management applications
    5.
    发明授权
    Maximum voltage selector for power management applications 有权

    公开(公告)号：US11073857B1

    公开(公告)日：2021-07-27

    申请号：US17039926

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K19/0185 ,  G05F1/575 ,  H03F3/45 ,  H03K19/20 ,  H03K17/687

    Abstract: A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.

    CIRCUITS AND METHODS FOR TRACKING MINIMUM VOLTAGE AT MULTIPLE SENSE POINTS
    7.
    发明申请
    CIRCUITS AND METHODS FOR TRACKING MINIMUM VOLTAGE AT MULTIPLE SENSE POINTS 有权

    公开(公告)号：US20220341975A1

    公开(公告)日：2022-10-27

    申请号：US17236227

    申请日：2021-04-21

    Applicant: NXP B.V.

    Inventor： Andre Luis Vilas Boas ,  Bruno Caceres Carrilho ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: G01R19/165 ,  H03K5/24 ,  H03K17/687 ,  G08B21/18

    Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.

    Temperature compensated auto tunable frequency locked loop oscillator
    8.
    发明授权
    Temperature compensated auto tunable frequency locked loop oscillator 有权

    公开(公告)号：US11437981B1

    公开(公告)日：2022-09-06

    申请号：US17218400

    申请日：2021-03-31

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Neil Edward Birns ,  Andre Gunther ,  Rob Cosaro

    IPC: H03K3/03 ,  H03K3/011

    Abstract: A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.

    Active N-Well Switching Circuit for Power Switches
    9.
    发明申请
    Active N-Well Switching Circuit for Power Switches 有权

    公开(公告)号：US20220103170A1

    公开(公告)日：2022-03-31

    申请号：US17039921

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K17/687 ,  H03K17/567

    Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

    Standby current reduction through a switching arrangement with multiple regulators
    10.
    发明授权
    Standby current reduction through a switching arrangement with multiple regulators 有权
    通过具有多个调节器的开关装置的待机电流降低

    公开(公告)号：US08954767B2

    公开(公告)日：2015-02-10

    申请号：US13888099

    申请日：2013-05-06

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Kevin Mahooti ,  Meng Hao

    IPC: G06F1/00 ,  G06F1/32 ,  G05F1/56 ,  H02M3/156

    CPC classification number: G06F1/3203 ,  G05F1/56 ,  H02M3/156

    Abstract: Consistent with an example embodiment, there is a power regulator arrangement with variable current capacity providing power from a power supply to a load having variable demand. As a load, a high-performance microprocessor has several modes of operation. At the highest speed setting, it demands a lot of current. At slower clock speeds and during state retention, the processor has a very low current consumption. Using a single regulator, the current efficiency may be very low during long standby periods. To increase the efficiency even at lower load currents, a scheme is based on parallel operation of multiple regulators having different load ranges, for example, a “low, “medium,” and “high” range regulators. Having knowledge of the load current profile, the regulators can be adjusted such that the peak of the efficiency curve matches the load profile of the regulator. The efficiency of the power regulator arrangement is enhanced throughout the range of power demanded by the load.

    Abstract translation: 与示例性实施例一致，存在具有可变电流容量的功率调节器装置，其从电源向具有可变需求的负载提供功率。 作为负载，高性能微处理器具有多种操作模式。 在最高速度设置下，需要大量的电流。 在较慢的时钟速度和状态保持期间，处理器具有非常低的电流消耗。 使用单个调节器，在长待机期间，电流效率可能非常低。 为了提高效率，即使在较低的负载电流下，一种方案是基于具有不同负载范围的多个稳压器的并联运行，例如“低”，“中”和“高”范围调节器。 了解负载电流曲线后，可以调整调节器，使得效率曲线的峰值与调节器的负载曲线相匹配。 在负载所需的功率范围内，功率调节器装置的效率得到提高。

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