公开(公告)号：US20230393639A1

公开(公告)日：2023-12-07

申请号：US17805652

申请日：2022-06-06

申请人： NXP B.V.

发明人： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

IPC分类号： G06F1/3212 ,  G06F1/3296

CPC分类号： G06F1/3212 ,  G06F1/3296

摘要： Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

公开(公告)号：US12099394B2

公开(公告)日：2024-09-24

申请号：US17805652

申请日：2022-06-06

申请人： NXP B.V.

发明人： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

IPC分类号： G06F1/32 ,  G06F1/3212 ,  G06F1/3296

CPC分类号： G06F1/3212 ,  G06F1/3296

摘要： Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

公开(公告)号：US11437981B1

公开(公告)日：2022-09-06

申请号：US17218400

申请日：2021-03-31

申请人： NXP B.V.

发明人： Domenico Liberti ,  Neil Edward Birns ,  Andre Gunther ,  Rob Cosaro

IPC分类号： H03K3/03 ,  H03K3/011

摘要： A temperature compensated, auto tunable, frequency locked loop oscillator includes, in one embodiment, an oscillator configured to generate a clock-signal with a frequency fclk based on a control voltage vc, and a frequency-to-voltage (f/v) converter coupled to the oscillator, which is configured to generate a first voltage vfb with a magnitude based on frequency fclk. A controller is also included and coupled between the oscillator and the f/v converter. The controller is configured to control the magnitude of the control voltage vc based on the first voltage vfb.