公开(公告)号：US20240305289A1

公开(公告)日：2024-09-12

申请号：US18311696

申请日：2023-05-03

Applicant: NXP B.V.

Inventor： Sapna Sharma ,  Sanjay Kumar Wadhwa ,  Neha Goel

IPC: H03K17/22 ,  H03K3/037 ,  H03K17/284

CPC classification number: H03K17/223 ,  H03K3/0377 ,  H03K17/284

Abstract: One example discloses a power on reset (POR) circuit, including: an input configured to receive a power supply voltage; a delay circuit configured to output a first signal to a set of logic circuits prior to a delay time; wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time; wherein the delay circuit includes a voltage drop device coupled to receive the power supply voltage, a switching device having an on-resistance and coupled to the voltage drop device, and a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time.