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公开(公告)号:US11277121B1
公开(公告)日:2022-03-15
申请号:US17161083
申请日:2021-01-28
Applicant: NXP B.V.
Inventor: Saurabh Goyal , Divya Tripathi , Sanjay Kumar Wadhwa
IPC: H03K17/687 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K3/356 , H03K19/003 , H03K17/10
Abstract: A level shifter includes a pull-down circuit, a pull-up circuit, a protection circuit, and an output generator. The pull-down circuit is configured to receive input voltages, and generate bias voltages. The input voltages are associated with a voltage domain. The pull-up circuit is configured to receive a supply voltage and generate control voltages. The protection circuit is configured to receive reference voltages, and control the generation of the bias voltages and the control voltages. The output generator is configured to receive at least one of the reference voltages, and at least one of the bias voltages and the control voltages, and generate output voltages that are able to reach minimum and maximum voltage levels of another voltage domain. Further, the output voltages remain unaffected by variations in process, voltage, and temperature.
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公开(公告)号:US11927493B2
公开(公告)日:2024-03-12
申请号:US17644212
申请日:2021-12-14
Applicant: NXP B.V.
Inventor: Saurabh Goyal , Sanjay Kumar Wadhwa , Firas N. Abughazaleh , Atul Kumar
Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.
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公开(公告)号:US11586238B1
公开(公告)日:2023-02-21
申请号:US17644356
申请日:2021-12-15
Applicant: NXP B.V.
Inventor: Robert Matthew Mertens , Ateet Omer , Sanjay Kumar Wadhwa , Charles Eric Seaberg
Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.
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公开(公告)号:US11581878B1
公开(公告)日:2023-02-14
申请号:US17450403
申请日:2021-10-08
Applicant: NXP B.V.
Inventor: Sanjay Kumar Wadhwa , Saurabh Goyal , Divya Tripathi
IPC: H03K19/00 , H03K19/0175 , H03K19/0185 , H03F3/45 , H03K3/356 , H03K17/10 , H03K5/156
Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.
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公开(公告)号:US20240305289A1
公开(公告)日:2024-09-12
申请号:US18311696
申请日:2023-05-03
Applicant: NXP B.V.
Inventor: Sapna Sharma , Sanjay Kumar Wadhwa , Neha Goel
IPC: H03K17/22 , H03K3/037 , H03K17/284
CPC classification number: H03K17/223 , H03K3/0377 , H03K17/284
Abstract: One example discloses a power on reset (POR) circuit, including: an input configured to receive a power supply voltage; a delay circuit configured to output a first signal to a set of logic circuits prior to a delay time; wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time; wherein the delay circuit includes a voltage drop device coupled to receive the power supply voltage, a switching device having an on-resistance and coupled to the voltage drop device, and a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time.
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公开(公告)号:US20230184594A1
公开(公告)日:2023-06-15
申请号:US17644212
申请日:2021-12-14
Applicant: NXP B.V.
Inventor: Saurabh Goyal , Sanjay Kumar Wadhwa , Firas N. Abughazaleh , Atul Kumar
Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.
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公开(公告)号:US11353910B1
公开(公告)日:2022-06-07
申请号:US17302399
申请日:2021-04-30
Applicant: NXP B.V.
Inventor: Sanjay Kumar Wadhwa , Ricardo Pureza Coimbra , Jaideep Banerjee
IPC: G05F3/26
Abstract: A bandgap voltage regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplifier, and a driver circuit. The PTAT circuit can include various transistors that output a corresponding control voltage. The amplifier generates another control voltage to compensate base-current variations associated with the transistors of the PTAT circuit. The control voltage is generated by the amplifier based on the control voltage outputted by the PTAT circuit, and one of a base-emitter voltage associated with a transistor of the PTAT circuit, a scaled down version of the control voltage outputted by the amplifier, and a scaled down version of the base-emitter voltage. The driver circuit outputs, based on a supply voltage and the control voltages outputted by the PTAT circuit, a reference voltage for driving a functional circuit.
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公开(公告)号:US20230361772A1
公开(公告)日:2023-11-09
申请号:US17662086
申请日:2022-05-05
Applicant: NXP B.V.
Inventor: Sanjay Kumar Wadhwa , Divya Tripathi , Saurabh Goyal , Alvin Leng Sun Loke , Manish Kumar Upadhyay
IPC: H03K17/687
CPC classification number: H03K17/6871
Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.
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公开(公告)号:US11378991B1
公开(公告)日:2022-07-05
申请号:US17304632
申请日:2021-06-23
Applicant: NXP B.V.
Inventor: Saurabh Goyal , Sanjay Kumar Wadhwa , Divya Tripathi
Abstract: A soft-start circuit for a voltage regulator includes a comparator and a delay circuit. The comparator compares an output voltage, that is generated by the voltage regulator, and a reference voltage to generate a comparison signal. Further, the delay circuit receives the reference voltage and a control signal that is outputted based on the comparison signal, and outputs and provides another reference voltage to the voltage regulator. During a start-up of the voltage regulator, the reference voltage outputted by the delay circuit is a delayed version of the reference voltage received by the delay circuit. Thus, the soft-start circuit mitigates an overshoot of the output voltage during the start-up. Further, on completion of the start-up, the reference voltage outputted by the delay circuit is equal to the reference voltage received by the delay circuit.
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