公开(公告)号：US20240305289A1

公开(公告)日：2024-09-12

申请号：US18311696

申请日：2023-05-03

Applicant: NXP B.V.

Inventor： Sapna Sharma ,  Sanjay Kumar Wadhwa ,  Neha Goel

IPC: H03K17/22 ,  H03K3/037 ,  H03K17/284

CPC classification number: H03K17/223 ,  H03K3/0377 ,  H03K17/284

Abstract: One example discloses a power on reset (POR) circuit, including: an input configured to receive a power supply voltage; a delay circuit configured to output a first signal to a set of logic circuits prior to a delay time; wherein the delay circuit is configured to output a second signal to the set of logic circuits after the delay time; wherein the delay circuit includes a voltage drop device coupled to receive the power supply voltage, a switching device having an on-resistance and coupled to the voltage drop device, and a capacitance device having a capacitance and coupled to the switching device; and wherein the on-resistance of the switching device and the capacitance of the capacitance device together are configured to set the delay time.

公开(公告)号：US11940832B2

公开(公告)日：2024-03-26

申请号：US17452602

申请日：2021-10-28

Applicant: NXP B.V.

Inventor： Matthias Rose ,  Maxim Kulesh ,  Neha Goel

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: A first error is determined between a bandgap reference output voltage of a bandgap reference circuit at a first temperature and a target voltage. A second temperature of the bandgap reference circuit is measured. A bandgap reference output voltage of the bandgap reference circuit is predicted at the second temperature and based on the first error. A second error is determined between the bandgap reference output voltage and the target voltage. A trim parameter of the bandgap reference circuit is determined based on the second error. The bandgap reference circuit is set with the trim parameter, where a third error between a bandgap reference output voltage of the bandgap reference with the trim parameter is less than the second error.

公开(公告)号：US20230139554A1

公开(公告)日：2023-05-04

申请号：US17452602

申请日：2021-10-28

Applicant: NXP B.V.

Inventor： Matthias Rose ,  Maxim Kulesh ,  Neha Goel

IPC: G05F3/30

Abstract: A first error is determined between a bandgap reference output voltage of a bandgap reference circuit at a first temperature and a target voltage. A second temperature of the bandgap reference circuit is measured. A bandgap reference output voltage of the bandgap reference circuit is predicted at the second temperature and based on the first error. A second error is determined between the bandgap reference output voltage and the target voltage. A trim parameter of the bandgap reference circuit is determined based on the second error. The bandgap reference circuit is set with the trim parameter, where a third error between a bandgap reference output voltage of the bandgap reference with the trim parameter is less than the second error.

公开(公告)号：US20240356543A1

公开(公告)日：2024-10-24

申请号：US18332522

申请日：2023-06-09

Applicant: NXP B.V.

Inventor： Henricus Cornelis Johannes Büthker ,  Jyotirmoy Ghosh ,  Piotr Gibas ,  Edwin Schapendonk ,  Neha Goel ,  Namith Vishnu N

IPC: H03K17/22 ,  H03K3/037

CPC classification number: H03K17/223 ,  H03K3/037

Abstract: One example discloses a power on reset (POR) circuit, wherein a first circuit is configured to un-couple a power supply input from a resistor divider when the voltage on a second end of the capacitor is above a first circuit threshold; a second circuit configured to couple the second end of the capacitor to the power supply input when a voltage on at least one tap point of the resistor divider is above a second circuit threshold; wherein the comparator is coupled to at least one of the tap points, the reference potential, and a POR output; and wherein the comparator is configured to ramp-up a POR signal on the POR output when a voltage on the at least one of the tap points is greater than the comparator threshold.