公开(公告)号：US20070046610A1

公开(公告)日：2007-03-01

申请号：US11500380

申请日：2006-08-08

申请人： Noboru Okuzono

发明人： Noboru Okuzono

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2320/0223 ,  G09G2320/0247

摘要： A driving method for a display apparatus including a plurality of pixels arranged in matrix along a line direction and a column direction implements sequential driving in the column direction by inverting a polarity of a plurality of pixels arranged in the line direction. The method includes driving a plurality of pixels arranged in an odd line, and driving a plurality of pixels arranged in an even line and in a column different from a column of the plurality of driven pixels in the odd line.

摘要翻译： 包括沿着线方向和列方向排列成矩阵的多个像素的显示装置的驱动方法通过使排列在行方向上的多个像素的极性反转来实现列方向上的顺序驱动。 该方法包括驱动布置在奇数行中的多个像素，并且驱动排列成奇数行中的多个驱动像素的偶数行和不同列的多个像素。

公开(公告)号：US08988124B2

公开(公告)日：2015-03-24

申请号：US13292133

申请日：2011-11-09

申请人： Masanao Yokoyama ,  Noboru Okuzono

发明人： Masanao Yokoyama ,  Noboru Okuzono

IPC分类号： H03K3/289 ,  H03K3/356 ,  H03K3/012 ,  H03K3/3562

CPC分类号： G09G3/3611 ,  G09G2310/0264 ,  G09G2310/08 ,  H03K3/012 ,  H03K3/356156 ,  H03K3/35625

摘要： An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

摘要翻译： 输入缓冲器根据第一控制时钟选择输出输入数据信号或输出高阻抗信号。 主触发器根据第二控制时钟选择输出从输入缓冲器接收的数据信号或保持当前输出的数据信号。 主从开关根据第二控制时钟选择输出高阻抗信号或输出从主触发器接收的数据信号。 从触发器根据第二控制时钟选择保持当前输出的数据信号或输出从主从交换机接收的数据信号。 时钟缓冲器输入第二控制时钟，并产生并输出第一控制时钟。

公开(公告)号：US07812752B2

公开(公告)日：2010-10-12

申请号：US12289266

申请日：2008-10-23

申请人： Hiroshi Tsuchi ,  Noboru Okuzono

发明人： Hiroshi Tsuchi ,  Noboru Okuzono

IPC分类号： H03M1/66

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  H03M1/661 ,  H03M1/68 ,  H03M1/76

摘要： A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.

摘要翻译： 数模转换器电路包括：第一子编码器，用于接收第一参考电压组并基于输入数字信号选择参考电压Vrk; 第二子编码器，用于接收第二参考电压组，并且基于所输入的数字信号选择参考电压Vr（k + 1）; 第三子编码器，用于接收第三参考电压组，并且基于所输入的数字信号选择参考电压Vr（k + 2）; 第四子编码器，用于接收由第一至第三子解码器中的相应的子编码器选择的参考电压，基于输入的数字信号选择这些参考电压中的两个（包括冗余选择相同的电压），并输出所选择的两个参考 电压; 以及放大器电路，用于接收由第四子解码器选择的两个参考电压并输出施加于两个参考电压的操作结果。

公开(公告)号：US20060232534A1

公开(公告)日：2006-10-19

申请号：US11431731

申请日：2006-05-10

申请人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

发明人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/2074 ,  G09G3/3607 ,  G09G3/3648

摘要： In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

摘要翻译： 在液晶显示装置中，布置在液晶面板101A上的每个单位像素p由多个像素p 1，p 2和p 3构成，像素p 1，p 2和p 3被分成 子像素p 11和p 12，子像素p 21和p 22以及子像素p 31和p 32。 液晶显示装置设置有用于驱动构成像素的子像素p 11，p 21和p 31以及子像素p 12，p 22和p 32的驱动器IC 201和202，使得不同的等级 可以给出 - 亮度值特性。 由此，可以进行多层次显示。

公开(公告)号：US06911967B2

公开(公告)日：2005-06-28

申请号：US10762501

申请日：2004-01-23

申请人： Noboru Okuzono ,  Koichi Koga

发明人： Noboru Okuzono ,  Koichi Koga

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G2320/0204 ,  G09G2320/0223

摘要： A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.

摘要翻译： 提供了具有低功耗的液晶显示器，并且防止水平条纹发生，而电路变得更加复杂。 当写入电压极性每多行反转时，在极性反转的n行中，由于漏极线的充电，漏极线波形的上升变钝。 在n + 1行中，由于通过n行的写入对漏极线进行了充电，因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此，在时钟信号的上升时，输出使能信号被激活，并且在开始写入的预定时间之后激活栅极线。 因此，在波形迟钝期间不进行写入，写入状态在所有扫描线上相同。

公开(公告)号：US07859268B2

公开(公告)日：2010-12-28

申请号：US11512351

申请日：2006-08-30

申请人： Noboru Okuzono ,  Takashi Morigami ,  Tsukasa Yasuda

发明人： Noboru Okuzono ,  Takashi Morigami ,  Tsukasa Yasuda

IPC分类号： G01R31/00 ,  G09G3/00

CPC分类号： G09G3/006 ,  G09G3/2007 ,  Y10S345/904

摘要： A test signal is supplied to a test switch provided between a D/A converter for selecting and outputting a gray scale voltage of the driving circuit and an amplifier for amplifying and supplying an output voltage at the D/A converter to set a test mode, and an output voltage of the D/A converter is directly measured by a measuring device through the test switch to measure an ON resistance of a gray scale voltage selection circuit of the D/A converter.

摘要翻译： 将测试信号提供给设置在用于选择和输出驱动电路的灰度电压的D / A转换器之间的测试开关和放大器，用于在D / A转换器处放大并提供输出电压以设置测试模式， 并且D / A转换器的输出电压由测量装置通过测试开关直接测量，以测量D / A转换器的灰度级电压选择电路的导通电阻。

公开(公告)号：US20070067693A1

公开(公告)日：2007-03-22

申请号：US11512351

申请日：2006-08-30

申请人： Noboru Okuzono ,  Takashi Morigami ,  Tsukasa Yasuda

发明人： Noboru Okuzono ,  Takashi Morigami ,  Tsukasa Yasuda

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G09G3/006 ,  G09G3/2007 ,  Y10S345/904

摘要： A test signal is supplied to a test switch provided between a D/A converter for selecting and outputting a gray scale voltage of the driving circuit and an amplifier for amplifying and supplying an output voltage at the D/A converter to set a test mode, and an output voltage of the D/A converter is directly measured by a measuring device through the test switch to measure an ON resistance of a gray scale voltage selection circuit of the D/A converter.

摘要翻译： 将测试信号提供给设置在用于选择和输出驱动电路的灰度电压的D / A转换器之间的测试开关和放大器，用于在D / A转换器处放大并提供输出电压以设置测试模式， 并且D / A转换器的输出电压由测量装置通过测试开关直接测量，以测量D / A转换器的灰度级电压选择电路的导通电阻。

公开(公告)号：US07116297B2

公开(公告)日：2006-10-03

申请号：US10413458

申请日：2003-04-14

申请人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

发明人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/2074 ,  G09G3/3607 ,  G09G3/3648

摘要： In a liquid crystal display device where each unit pixel p arranged on a liquid crystal panel 101A is constituted by a plurality of pixels p1, p2, and p3, the pixels p1, p2, and p3 are divided into sub-pixels p11 and p12, sub-pixels p21, and p22, and sub-pixels p31 and p32, respectively. The liquid crystal display device is provided with driver ICs 201 and 202 for driving the sub-pixels p11, p21, and p31, and the sub-pixels p12, p22, and p32 constituting the pixels so that different gradation-brightness value characteristics may be given. Due to this, multi-gradation display can be performed.

摘要翻译： 在液晶显示装置中，布置在液晶面板101A上的每个单位像素p由多个像素p 1，p 2和p 3构成，像素p 1，p 2和p 3被分成 子像素p 11和p 12，子像素p 21和p 22以及子像素p 31和p 32。 液晶显示装置设置有用于驱动构成像素的子像素p 11，p 21和p 31以及子像素p 12，p 22和p 32的驱动器IC 201和202，使得不同的等级 可以给出 - 亮度值特性。 由此，可以进行多层次显示。

公开(公告)号：US06727878B2

公开(公告)日：2004-04-27

申请号：US09772864

申请日：2001-01-31

申请人： Noboru Okuzono ,  Koichi Koga

发明人： Noboru Okuzono ,  Koichi Koga

IPC分类号： G09G336

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G2320/0204 ,  G09G2320/0223

摘要： A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.

摘要翻译： 提供了具有低功耗的液晶显示器，并且防止水平条纹发生，而电路变得更加复杂。 当写入电压极性每多行反转时，在极性反转的n行中，由于漏极线的充电，漏极线波形的上升变钝。 在n + 1行中，由于通过n行的写入对漏极线进行了充电，因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此，在时钟信号的上升时，输出使能信号被激活，并且在开始写入的预定时间之后激活栅极线。 因此，在波形迟钝期间不进行写入，写入状态在所有扫描线上相同。

公开(公告)号：US06559822B2

公开(公告)日：2003-05-06

申请号：US09299025

申请日：1999-04-26

申请人： Noboru Okuzono

发明人： Noboru Okuzono

IPC分类号： G09G336

CPC分类号： G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/02

摘要： An active matrix-type liquid crystal display device which is capable of realizing a dot inversion driving by disposing H drivers on both sides of the liquid crystal panel, while using existing H driver circuits which output odd output data and even output data at opposite polarities to each other. The first and second H drivers, which output odd output data and even output data at opposite polarities to each other, are disposed facing each other on both sides of the liquid crystal panel, in order to realize an active matrix-type liquid crystal display device which is conducted by the dot inversion driving. Data electrodes of said liquid crystal display device are taken out for every two lines or every integer times of two lines and the thus taken out data lines are connected alternately to the first and second driver circuits.

摘要翻译： 一种有源矩阵型液晶显示装置，其能够通过在液晶面板的两侧配置H驱动器来实现点反转驱动，同时使用输出奇数输出数据的现有H驱动电路，甚至以相反极性输出数据 彼此。 为了实现有源矩阵型液晶显示装置，第一和第二H驱动器将输出奇数输出数据，甚至以相反的极性输出数据彼此面对地设置在液晶面板的两侧 其通过点反转驱动进行。 所述液晶显示装置的数据电极每两行或每两行的整数倍被取出，这样取出的数据线交替地连接到第一和第二驱动电路。