公开(公告)号：US20220131915A1

公开(公告)日：2022-04-28

申请号：US17081464

申请日：2020-10-27

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea ENRICI ,  Faycal AIT AOUDIA ,  Julien LALLET

IPC: H04L29/06 ,  G06F30/34

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network-based apparatus to: select at least a first bitstream from a central repository based on an indicator associated with a probability of concurrent, simultaneous or future execution of the first bitstream and a second bitstream at a network node, each of the first bitstream and the second bitstream including programming information for a device at the network node, the indicator being based on an embedding matrix mapping at least a subset of bitstreams in the central repository to an N-dimensional vector of real numbers; and output the first bitstream to the network node for storage and execution upon request.

公开(公告)号：US20230315634A1

公开(公告)日：2023-10-05

申请号：US18329277

申请日：2023-06-05

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea ENRICI ,  Julien LALLET

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0871 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0871 ,  G06F13/1668

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

公开(公告)号：US20220147457A1

公开(公告)日：2022-05-12

申请号：US17095109

申请日：2020-11-11

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea ENRICI ,  Julien LALLET

IPC: G06F12/0811 ,  G06F12/0813 ,  G06F12/0871 ,  G06F12/0804 ,  G06F13/16

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

公开(公告)号：US20220327063A1

公开(公告)日：2022-10-13

申请号：US17224622

申请日：2021-04-07

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea ENRICI ,  Julien LALLET

IPC: G06F12/1036 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17756 ,  G06F12/1009 ,  H03K19/1776

Abstract: At least one example embodiment provides a programmable logic device comprising: a plurality of reconfigurable slots programmed to execute functions requested by a plurality of users, the plurality of reconfigurable slots allocated among the plurality of users; a memory divided into a plurality of memory segments, the plurality of memory segments allocated among the plurality of reconfigurable slots; and a memory management circuit configured to dynamically adjust the plurality of memory segments based on at least one of activity or memory requirements of the plurality of reconfigurable slots.